CY7C006A-20AI Cypress Semiconductor Corp, CY7C006A-20AI Datasheet

CY7C006A-20AI

Manufacturer Part Number
CY7C006A-20AI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C006A-20AI

Density
128Kb
Access Time (max)
20ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
14b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
2
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Word Size
8b
Number Of Words
16K
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C006A-20AI
Manufacturer:
CY
Quantity:
8
Part Number:
CY7C006A-20AI
Manufacturer:
CYPRESS
Quantity:
14
Part Number:
CY7C006A-20AI
Manufacturer:
CYP
Quantity:
628
Cypress Semiconductor Corporation
Document #: 38-06045 Rev. *D
Features
CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
• True dual-ported memory cells which allow
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
Notes:
A
A
CE
OE
R/W
SEM
BUSY
INT
1. See page 7 for Load Conditions.
2. I/O
3. BUSY is an output in master mode and an input in slave mode.
4. A
R/W
CE
OE
I/O
simultaneous access of the same memory location
— Active: I
— Standby: I
0L
0L
L
0L
L
L
L
–A
–A
L
0
L
–A
L
0
L
–I/O
–I/O
L
13/14L
13/14L
13
[3]
for 16K; A
7
7/8L
[4]
[4]
for x8 devices; I/O
[2]
CC
SB3
= 180 mA (typical)
0
–A
= 0.05 mA (typical)
14
14/15
for 32K devices.
8/9
0
–I/O
[1]
/15/20 ns
8
Address
Decode
for x9 devices.
14/15
198 Champion Court
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
• Pb-Free packages available
Master/Slave chip select when using more than one
device
between ports
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
Control
I/O
Dual-Port Static RAM
San Jose
Dual-Port Static RAM
32K/16K x 8, 32K x 9
Address
Decode
,
14/15
CA 95134-1709
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Revised August 11, 2005
14/15
8/9
I/O
A
A
408-943-2600
0R
0R
0R
[3]
–A
–A
–I/O
BUSY
SEM
R/W
13/14R
13/14R
R/W
[2]
INT
OE
CE
OE
CE
7/8R
R
R
R
[4]
R
R
R
R
R
R
[4]
[+] Feedback

Related parts for CY7C006A-20AI

CY7C006A-20AI Summary of contents

Page 1

... Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Pin select for Master or Slave • Commercial temperature range • Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A) • Pb-Free packages available I/O ...

Page 2

... Notes: 5. This pin is I/O for CY7C017A only connect pin for 16K devices. 14 Document #: 38-06045 Rev. *D 68-Pin PLCC Top View CY7C006A (16K CY7C007A (32K CY7C017A (32K 80-Pin TQFP Top View CY7C007A (32K x 8) CY7C016A (16K X 9) CY7C006A/CY7C007A CY7C016A/CY7C017A ...

Page 3

... Selection Guide Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for I (mA) (Both Ports CMOS Level) SB3 Document #: 38-06045 Rev. *D 64-Pin TQFP Top View CY7C006A (16K CY7C006A CY7C007A CY7C016A CY7C017A [1] -12 12 ...

Page 4

... An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C006A, CY7C007A, and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. Write Operation Data must be set up for a duration R/W in order to guarantee a valid write ...

Page 5

... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t ...

Page 6

... Ind. Com’l. 125 205 Ind. Com’l. 0.05 0.5 Ind. Com’l. 115 185 L Ind. Test Conditions ° MHz 5.0V CC CY7C006A/CY7C007A CY7C016A/CY7C017A [8] .........................................–0.5V to +7.0V Ambient Temperature V CC ° ° 5V ± 10 +70 C -15 -20 Typ. Max. Min. Typ. Max. Unit 2.4 V 0.4 ...

Page 7

... TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [11] 3.0V 10% GND ≤ Capacitance (pF) (b) Load Derating Curve CY7C006A/CY7C007A CY7C016A/CY7C017A 893Ω OUTPUT 347Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% ≤ ...

Page 8

... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. Test conditions used are Load 2. 19. For 15 ns industrial parts t Min. is 0.5 ns. HD Document #: 38-06045 Rev. *D CY7C006A/CY7C007A CY7C016A/CY7C017A [12] CY7C006A CY7C007A CY7C016A CY7C017A [1] –12 –15 Min. Max. ...

Page 9

... SEM Address Access Time SAA Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...

Page 10

... DATA OUT Notes: 25. Address valid prior to or coincident with CE transition LOW. 26. To access RAM SEM = access semaphore Document #: 38-06045 Rev. *D [22, 25, 26] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C006A/CY7C007A CY7C016A/CY7C017A t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...

Page 11

... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06045 Rev. *D [27, 28, 29, 30 [30] t PWE [32] t HZWE t SD [27, 28, 29, 34 SCE LOW CE or SEM PWE CY7C006A/CY7C007A CY7C016A/CY7C017A [32] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...

Page 12

... SPS Document #: 38-06045 Rev. *D [35 VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [36, 37, 38] MATCH t SPS MATCH = CE = HIGH CY7C006A/CY7C007A CY7C016A/CY7C017A t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...

Page 13

... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW Document #: 38-06045 Rev. *D [39 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C006A/CY7C007A CY7C016A/CY7C017A BHA t BDD t DDD VALID Page [+] Feedback ...

Page 14

... BUSY will be asserted. PS Document #: 38-06045 Rev. *D [40] ADDRESS MATCH BLC ADDRESS MATCH BLC [40 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C006A/CY7C007A CY7C016A/CY7C017A t BHC t BHC Page [+] Feedback ...

Page 15

... INT L Notes: 41. t depends on which enable pin ( depends on which enable pin (CE INS INR L Document #: 38-06045 Rev WRITE 7FFF [41 [42] t INR t WC WRITE 7FFE [41 [42] t INR ) is deasserted first R asserted last. L CY7C006A/CY7C007A CY7C016A/CY7C017A t RC READ 7FFF t RC READ 7FFE Page [+] Feedback ...

Page 16

... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C006A/CY7C007A CY7C016A/CY7C017A Operation Right Port INT R R 0R–14R R [44 [43] L ...

Page 17

... Ordering Information 16K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C006A-12AC CY7C006A-12JC 15 CY7C006A-15AC CY7C006A-15AXC CY7C006A-15JC 20 CY7C006A-20AC CY7C006A-20AXC CY7C006A-20AI CY7C006A-20AXI CY7C006A-20JC CY7C006A-20JXC 32K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C007A-12AC CY7C007A-12JC 15 CY7C007A-15AC CY7C007A-15JC 20 CY7C007A-20AC CY7C007A-20JC CY7C007A-20JXC 16K x9 Asynchronous Dual-Port SRAM Speed ...

Page 18

... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Document #: 38-06045 Rev. *D CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85046-*B Page [+] Feedback ...

Page 19

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 80-Pin Thin Plastic Quad Flat Pack A80 CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85065-*B ...

Page 20

... Power up requirements added to Maximum Ratings Information Removed cross information from features section Removed I-Temp versions for both packages, since they are not valid part numbers. Included Pb-Free Logo Included package: CY7C006A-20AI Included Pb-Free packages: CY7C006A-15AXC, CY7C006A-20AXC, CY7C006A-20AXI, CY7C006A-20JXC, CY7C007A-20JXC, CY7C016A-15AXC Page ...

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