CY7C008V-25AC Cypress Semiconductor Corp, CY7C008V-25AC Datasheet
CY7C008V-25AC
Specifications of CY7C008V-25AC
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CY7C008V-25AC Summary of contents
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... CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • ...
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... Note: 4. This pin is NC for CY7C008V. Document #: 38-06044 Rev. *C Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port ...
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... CY7C019V (128K x 9) CY7C018V (64K CY7C008V/009V CY7C008V/009V CY7C018V/019V CY7C018V/019V -15 - 125 120 µA 10 µA CY7C008V/009V CY7C018V/019V A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R [5] 64 A16R 63 GND CE0R 57 CE1R 56 SEMR 55 R/WR 54 OER 53 GND 52 GND CY7C008V/009V CY7C018V/019V -25 Unit 25 ns 115 µA µA Page [+] Feedback ...
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... DC Input Voltage ..................................... –0. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V ° ° Latch-Up Current .................................................... >200 +150 C Operating Range ° ° +125 C Range Commercial +0.5V CC [7] Industrial CY7C008V/009V CY7C018V/019V ≤ V ≥ V and –A for 128K devices –I/O for x9 +0.5V ...
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... MHz 3. 250Ω TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ CY7C008V/009V CY7C018V/019V CY7C008V/009V CY7C018V/019V -20 -25 Unit 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 –5 5 –5 5 –10 10 –10 10 120 175 115 165 140 195 ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. Test conditions used are Load 1. Document #: 38-06044 Rev. *C [10] CY7C008V/009V CY7C018V/019V -15 -20 Min. Max. Min. Max less than t and t is less than t . HZCE LZCE HZOE LZOE CY7C008V/009V CY7C018V/019V -25 Min. Max. Unit time. SCE Page [+] Feedback ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C008V/009V and CY7018V/019V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, ...
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... Address valid prior to or coincident with CE transition LOW. 23. To access RAM SEM = access semaphore Document #: 38-06044 Rev. *C [19, 20, 21 DATA VALID [19, 22, 23] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C008V/009V CY7C018V/019V t OHA t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06044 Rev. *C [24, 25, 26, 27 [27] t PWE [29] t HZWE t SD [24, 25, 26, 31 SCE LOW CE or SEM PWE CY7C008V/009V CY7C018V/019V [29] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06044 Rev. *C [32] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [33, 34, 35] MATCH t SPS MATCH = CE = HIGH CY7C008V/009V CY7C018V/019V t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW Document #: 38-06044 Rev. *C [36 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C008V/009V CY7C018V/019V BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06044 Rev. *C [37] ADDRESS MATCH BLC ADDRESS MATCH BLC [37 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C008V/009V CY7C018V/019V t BHC t BHC Page [+] Feedback ...
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... R 39 depends on which enable pin (CE INS INR L Document #: 38-06044 Rev [38 (1FFFF for CY7C009V/19V) [39] t INR t WC [38 (1FFFF for CY7C009V/19V) [39] t INR ) is deasserted first R asserted last. L CY7C008V/009V CY7C018V/019V t RC READ FFFF t RC READ 1FFE Page [+] Feedback ...
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... Architecture The CY7C008V/009V and CY7018V/019V consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C008V/009V CY7C018V/019V Operation Right Port INT R R 0R–16R R [42 [41] L ...
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... Ordering Information 64K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C008V-15AC 20 CY7C008V-20AC 25 CY7C008V-25AC CY7C008V-25AXC 64K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C018V-15AC 20 CY7C018V-20AC 25 CY7C018V-25AC 128K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C009V-15AC CY7C009V-15AXC 20 CY7C009V-20AC CY7C009V-20AI CY7C009V-20AXI 25 CY7C009V-25AC CY7C009V-25AXC 128K x9 3.3V Asynchronous Dual-Port SRAM ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C008V/009V CY7C018V/019V ...
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... Document History Page Document Title: CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM Document Number: 38-06044 Issue Orig. of REV. ECN NO. Date Change ** 110192 09/29/01 SZV *A 113541 04/15/02 OOR *B 122294 12/27/02 RBI *C 393440 See ECN YIM Document #: 38-06044 Rev. *C Description of Change Change from Spec number: 38-00669 to 38-06044 Change pin 85 from BUSYL to BUSYR (pg ...