CY7C128A-45DMB Cypress Semiconductor Corp, CY7C128A-45DMB Datasheet

no-image

CY7C128A-45DMB

Manufacturer Part Number
CY7C128A-45DMB
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C128A-45DMB

Density
16Kb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
11b
Package Type
CDIP
Operating Temp Range
-55C to 125C
Number Of Ports
1
Supply Current
125mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Military
Mounting
Through Hole
Pin Count
24
Word Size
8b
Number Of Words
2K
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C128A-45DMB
Manufacturer:
CYP
Quantity:
900
Part Number:
CY7C128A-45DMB
Manufacturer:
TI
Quantity:
650
Part Number:
CY7C128A-45DMB
Manufacturer:
CYP
Quantity:
1 203
Cypress Semiconductor Corporation
Document #: 38-05028 Rev. *A
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
• Low active power
• Low standby power
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
• Available in Pb-free and non Pb-free 24-pin Molded
— 15 ns
— 660 mW (commercial)
— 110 mW (20 ns)
static discharge
SOJ, non Pb-free 24-pin (300-Mil) Molded DIP
Logic Block Diagram
CE
WE
OE
A
A
A
A
A
A
A
10
9
8
7
6
5
4
A
3
INPUT BUFFER
128 x 16 x 8
DECODER
COLUMN
ARRAY
A
2
A
1
A
0
POWER
DOWN
198 Champion Court
Functional Description
The CY7C128A is a high-performance CMOS static RAM
organized as 2048 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), and active
LOW Output Enable (OE) and tri-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
memory location specified on the address pins (A
A
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
The I/O pins remain in high-impedance state when Chip
Enable (CE) or Output Enable (OE) is HIGH or Write Enable
(WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
10
).
C128A–1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
San Jose
,
Pin Configurations
GND
I/O
I/O
I/O
CA 95134-1709
A
A
A
A
A
A
A
A
7
2
1
0
0
1
2
6
5
4
3
2K x 8 Static RAM
1
2
3
4
5
6
7
8
9
10
11
12
DIP/SOJ
Top View
0
7C128A
through I/O
Revised August 3, 2006
24
23
22
21
20
19
18
17
16
15
14
13
WE
V
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
7
CC
8
9
10
) is written into the
CY7C128A
7
6
5
4
3
408-943-2600
C128A–2
0
through

Related parts for CY7C128A-45DMB

CY7C128A-45DMB Summary of contents

Page 1

... I/O pins. The I/O pins remain in high-impedance state when Chip Enable (CE) or Output Enable (OE) is HIGH or Write Enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity. I/O 0 I/O 1 I/O ...

Page 2

... Min., I –4 Min 8 2.2 –0.5 < V – < V – Max OUT , CE > IH >V –0.3V > V –0.3V CC < 0.3V IN CY7C128A -20 - 120 120 20 20 Ambient Temperature ° ° +70 C -20 -35, -45 Max. Min. Max. Min. 2.4 2.4 0.4 0.4 V 2 0.8 –0.5 0.8 – ...

Page 3

... JIG AND (b) SCOPE C128A–4 [2, 5] -15 -20 Min. Max. Min less than t for any given device. HZCE LZCE CY7C128A Max ALL INPUT PULSES 3.0V 90% 90% 10% GND ≤ Equivalent to: THÉ VENIN EQUIVALENT 167Ω OUTPUT -35 -45 Max. Min. Max. Min. Max ...

Page 4

... Device is continuously selected. OE 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05028 Rev OHA t RC ACE t DOE LZOE 50 SCE PWE DATA t HZWE . IL CY7C128A DATA VALID t HZOE t HZCE IMPEDANCE DATA VALID VALID IN t LZWE HIGH IMPEDANCE C128A–6 HIGH C128A–7 C128A– ...

Page 5

... Notes: 12. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write. 13 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05028 Rev SCE PWE t SD DATA VALID IN t HZWE CY7C128A HIGH IMPEDANCE C128A–9 Page ...

Page 6

... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15 25°C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) CY7C128A OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. 5° 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs ...

Page 7

... Ordering Information Speed (ns) Ordering Code 15 CY7C128A-15PC CY7C128A-15VC CY7C128A-15VXC 20 CY7C128A-20VXC 35 CY7C128A-35VC 45 CY7C128A-45PC Please contact local sales representative regarding availability of these parts Package Diagrams Document #: 38-05028 Rev. *A Package Diagram Package Type 51-85013 24-pin (300-Mil) Molded DIP 51-85030 24-pin Molded SOJ 24-pin Molded SOJ 51-85030 ...

Page 8

... SOJ (51-85030) PIN DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088 0.291[7.39] 0.330[8.38] PACKAGE WEIGHT 0.75gms 0.300[7.62] 0.350[8.89] 24 SEATING PLANE 0.120[3.05] 0.140[3.55] 0.004[0.10] 0.025[0.63] MIN. CY7C128A MIN. MAX. PART # V24.3 STANDARD PKG. VZ24.3 LEAD FREE PKG. 0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91] 51-85030-*B Page ...

Page 9

... Document History Page Document Title: CY7C128A Static RAM Document Number: 38-05028 Issue REV. ECN NO. Date ** 106814 09/10/01 *A 493543 See ECN Document #: 38-05028 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00094 to 38-05028 NXR Removed 25 ns speed bin Removed Military Operating Range ...

Related keywords