IDT7MMV4101S10BG IDT, Integrated Device Technology Inc, IDT7MMV4101S10BG Datasheet

no-image

IDT7MMV4101S10BG

Manufacturer Part Number
IDT7MMV4101S10BG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT7MMV4101S10BG

Density
3Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
SDR
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
BGA
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
295mA
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
119
Word Size
24b
Number Of Words
128K
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT7MMV4101S10BG
Manufacturer:
IDT
Quantity:
503
©2003 Integrated Device Technology, Inc.
Features
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
Pin Names
Pin Configuration
4
7
5
3
2
1
6
High density 3 megabit 3.3V static RAM
Low profile 119 lead, 14mm x 22mm
BGA (Ball Grid Array)
Fast RAM access times: 10,12,15ns
Single 3.3V power supply
Multiple Vcc & GND pins for maximum noise immunity
Inputs/outputs directly LVTTL compatible
Commercial (0
temperature options
– Commercial: 10 / 12 / 15 ns
– Industrial: 12 / 15 ns
A0
A2
A1
NC
A3
A
A4
NC
I/O
A
GND
V
0
WE
CS
OE
NC
0
A5
NC
CC
CS
A6
A7
B
-
NC
A8
-
16
23
O
NC
NC
NC
I/O12
C
I/O0
NC
NC
C to +70
GND
VCC
GND
VCC
GND
I/O1
I/O13
D
O
C) Industrial (-40
GND
VCC
GND
VCC
GND
I/O2
I/O14
E
Data Inputs/Outputs
Output Enable
Write Enable
Chip Select
No Connect
Addresses
VCC
GND
GND
Ground
I/O3
GND
VCC
I/O15
Power
F
O
C to +85
GND
VCC
VCC
I/O4
GND
GND
I/O16
128K x 24 Three Megabit
3.3V CMOS Static RAM
G
VCC
GND
GND
GND
I/O5
VCC
I/O17
O
Top View
4083 tbl 01
C)
H
GND
NC
VCC
VCC
GND
GND
NC
J
1
multilayer laminate substrate using three 3.3V, 128K x 8 (IDT71V124)
static RAMS encapsulated in a Ball Grid Array (BGA).
ration allows 119 leads to be placed on a package 14mm by 22mm. At a
maximum of 3.5mm high, this low-profile surface mount package is ideal
for ultra dense systems.
operate from a single 3.3V supply. Full asynchronous circuitry requires
no clocks or refresh for operation and provides equal access and cycle
times for ease of use.
Functional Block Diagram
Description
A
I/O18
I/O6
VCC
GND
VCC
WE
GND
GND
0-16
The IDT7MMV4101 is packaged in a plastic BGA. The BGA configu-
CS
OE
The IDT7MMV4101 is a three megabit static RAM constructed on an
All inputs and outputs of the IDT7MMV4101 are LVTTL compatible and
K
17
I/O19
GND
VCC
GND
I/O7
GND
VCC
L
128K x 8
VCC
GND
I/O20
I/O8
GND
GND
VCC
SRAM
M
I/O
0-7
8
I/O9
GND
VCC
GND
VCC
GND
I/O21
N
I/O10
VCC
GND
GND
GND
VCC
I/O22
128K x 8
P
SRAM
I/O
8-15
IDT7MMV4101
8
I/O11
NC
NC
NC
NC
NC
I/O23
JANUARY 2003
R
NC
A12
A11
WE
A10
A9
NC
T
128K x 8
SRAM
I/O
A14
A13
NC
4083 drw 01
16-23
U
A15
OE
4083 drw 02
DSC-4083/05
NC
A16
8
,
,

Related parts for IDT7MMV4101S10BG

IDT7MMV4101S10BG Summary of contents

Page 1

... GND VCC GND I/O15 I/O16 I/O17 NC I/O18 I/O19 Top View 1 IDT7MMV4101 128K x 8 128K x 8 128K x 8 SRAM SRAM SRAM 8 8 I/O I/O I/O 16-23 0-7 8-15 4083 drw 01 I/O8 I/O9 I/O10 I/O11 NC NC VCC GND VCC NC A12 A16 GND VCC ...

Page 2

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Capacitance (T = +25° 1.0MHz) A (1) Symbol Parameter Conditions C Input Capacitance I/O Capacitance V I/O OUT NOTE: 1. This parameter is guaranteed ...

Page 3

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 216 Ω Figure 1. Output Load GND to 3.0V 3ns ...

Page 4

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM AC Electrical Characteristics (V = 3.3V ±10%) CC Symbol Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip ...

Page 5

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Timing Waveform of Read Cycle No. 1 ADDRESS OE CS HIGH IMPEDANCE DATA OUT Timing Waveform of Read Cycle No. 2 ADDRESS DATA PREVIOUS DATA OUT NOTES ...

Page 6

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS (4) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ...

Page 7

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Package Dimensions 22.0 + 0.1 TOP VIEW NOTES: 1. All dimensions are in mm. Ordering Information IDT XXXXX X X Device Power Speed Type Commercial and Industrial Temperature Ranges Q ...

Page 8

IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Datasheet History 09/18/00 Add datasheet history Pg. 2 Reduce I 01/07/03 Changed datasheet from Prelininary to final release CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The ...

Related keywords