IDT71321SA55JG IDT, Integrated Device Technology Inc, IDT71321SA55JG Datasheet

IDT71321SA55JG

Manufacturer Part Number
IDT71321SA55JG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71321SA55JG

Density
16Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
11b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
2K
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71321SA55JG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71321SA55JG
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT71321SA55JGI
Manufacturer:
IDT
Quantity:
4
Features
Functional Block Diagram
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
2. Open drain output: requires pullup resistor of 270Ω.
©2008 Integrated Device Technology, Inc.
I/O
High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
– IDT71321/421LA
Two INT flags for port-to-port communications
IDT71421 (SLAVE): BUSY is input.
0L
Active: 325mW (typ.)
Standby: 5mW (typ.)
Active: 325mW (typ.)
Standby: 1mW (typ.)
BUSY
- I/O
R/W
INT
A
OE
CE
A
10L
0L
7L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
CE
OE
L
L
L
11
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
Control
I/O
ARBITRATION
INTERRUPT
MEMORY
ARRAY
LOGIC
and
1
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Control
I/O
11
Decoder
Address
CE
OE
R/W
R
R
R
IDT71321SA/LA
IDT71421SA/LA
OCTOBER 2008
2691 drw 01
OE
CE
R/W
I/O
BUSY
A
A
INT
10R
0R
0R
R
R
R
DSC-2691/13
R
(2)
-I/O
R
(1,2)
7R

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IDT71321SA55JG Summary of contents

Page 1

Features High-speed access – Commercial: 20/25/35/55ns (max.) – Industrial: 25/55ns (max.) Low-power operation – IDT71321/IDT71421SA — Active: 325mW (typ.) — Standby: 5mW (typ.) – IDT71321/421LA — Active: 325mW (typ.) — Standby: 1mW (typ.) Two INT flags for port-to-port communications Functional ...

Page 2

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Description The IDT71321/IDT71421 are high-speed Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a ...

Page 3

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Capacitance (1) (TA = +25° 1.0MHz) TQFP Only Symbol Parameter Conditions C Input Capacitance IN C Output Capacitance V OUT NOTES: 1. This parameter is ...

Page 4

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating CC L Current Outputs Disabled (2) (Both Ports ...

Page 5

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (V Symbol Parameter ( Input Leakage Current LI ( Output Leakage Current ...

Page 6

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 775Ω Figure 1. AC Output Test Load ...

Page 7

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access ...

Page 8

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Timing Waveform of Read Cycle No. 1, Either Side ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT NOTES and ...

Page 9

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temeprature and Supply Voltage Range Symbol WRITE CYCLE (2) t Write Cycle Time WC t Chip Enable to End-of-Write EW t ...

Page 10

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) ADDRESS R/W DATA (4) OUT DATA IN Timing Waveform of Write Cycle ...

Page 11

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (For MASTER 71321) BUSY Access Time from Address t BAA BUSY Disable Time ...

Page 12

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT"B" NOTES: 1. ...

Page 13

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" AND "B" CE "B" (2) t APS CE "A" BUSY "A" Timing Waveform of BUSY Arbritration ...

Page 14

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time ...

Page 15

IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Truth Tables Truth Table I. Non-Contention Read/Write Control (1) Left or Right Port CE OE R ...

Page 16

... R memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation ...

Page 17

... TQFP (PN64-1) 64-pin STQFP (PP64-1) Commercial Only Commercial & Industrial Speed in nanoseconds Commercial Only Commercial & Industrial Low Power Standard Power 16K (2K x 8-Bit) MASTER Dual-Port SRAM w/ Interrupt 16K (2K x 8-Bit) SLAVE Dual-Port SRAM w/ Interrupt for Tech Support: 408-284-2794 DualPortHelp@idt.com , 2691 drw 17 ...

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