IDT70V24L25PFI IDT, Integrated Device Technology Inc, IDT70V24L25PFI Datasheet
IDT70V24L25PFI
Specifications of IDT70V24L25PFI
Related parts for IDT70V24L25PFI
IDT70V24L25PFI Summary of contents
Page 1
Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access IDT70V35/34 – Commercial: 15/20/25ns (max.) – Industrial: 20ns IDT70V25/24 – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25ns Low-power operation – IDT70V35/34S – IDT70V35/34L Active: 430mW ...
Page 2
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Description The IDT70V35/34 (IDT70V25/24 high-speed 8/ (8/4K x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de- signed to be used as a stand-alone ...
Page 3
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Pin Configurations (1,2,3,4) 06/24/04 Index 100 ...
Page 4
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Pin Configurations (1,2,3,4) 06/11/ I/O I/O I I/O I/O I/O 10L I/O I/O ...
Page 5
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Pin Configurations (1,2,3,4) 06/08/04 INDEX I I I/O 10L 14 ...
Page 6
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Pin Names Left Port Right Port CE CE Chip Enable L R R/W R/W Read/Write Enable Output Enable L R (1) (1) A ...
Page 7
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature T Junction Temperature JN ...
Page 8
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34 Symbol Parameter Dynamic Operating , Outputs Disabled DD IL SEM ...
Page 9
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V25/24 Symbol Parameter Dynamic Operating , Outputs Open DD IL SEM ...
Page 10
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34 Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA ...
Page 11
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V25/24 Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA ...
Page 12
... IL IL the entire t time The specification for t must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH voltage and temperature, the actual t will always be smaller than the actual 'X' in part number indicates power rating (S or L). ...
Page 13
... IL IL the entire t time The specification for t must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH voltage and temperature, the actual t will always be smaller than the actual 'X' in part number indicates power rating (S or L). ...
Page 14
... LOW during R/W controlled write cycle, the write pulse width must be the larger HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as placed on the bus for the required t DW the specified access SRAM and SEM = ...
Page 15
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side A -A VALID ADDRESS 0 2 SEM I R/W OE NOTES ...
Page 16
... Write Pulse to Data Delay WDD t Write Data Valid to Read Data Delay DDD NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M )" ensure that the earlier of the two ports wins calculated parameter and is the greater BDD 4 ...
Page 17
... Write Pulse to Data Delay WDD t Write Data Valid to Read Data Delay DDD NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M )" ensure that the earlier of the two ports wins calculated parameter and is the greater BDD 4 ...
Page 18
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES: must be met for both master BUSY input (slave) and output (master ...
Page 19
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34 Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR ...
Page 20
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. ...
Page 21
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Truth Table III — Interrupt Flag Left Port 12L 1FFF ...
Page 22
... High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM BUSY L Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs. Functional Description The IDT70V35/34 (IDT70V25/24) provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory ...
Page 23
... How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “ ...
Page 24
... Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V35/34 (IDT70V25/24)’s Dual-Port SRAM. Say the SRAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory ...
Page 25
IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/ (8/4K x 16) Dual-Port Static RAM Ordering Information A XXXXX A 999 A Device Power Speed Package Step Type NOTES: 1. Contact your local sales office for Industrial temp range for other speeds, ...