CY7C019V-20AC Cypress Semiconductor Corp, CY7C019V-20AC Datasheet

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CY7C019V-20AC

Manufacturer Part Number
CY7C019V-20AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C019V-20AC

Density
1.125Mb
Access Time (max)
20ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
175mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
9b
Number Of Words
128K
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C019V-20AC
Manufacturer:
CY
Quantity:
50
Part Number:
CY7C019V-20AC
Manufacturer:
CYPRESS
Quantity:
234
Cypress Semiconductor Corporation
Document #: 38-06044 Rev. *C
Features
Notes:
CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9
Dual-Port Static RAM
1. I/O
2. A
3. BUSY is an output in master mode and an input in slave mode.
• True Dual-Ported memory cells which allow simulta-
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
A
A
CE
OE
R/W
SEM
BUSY
INT
R/W
CE
CE
OE
I/O
neous access of the same memory location
— Active: I
— Standby: I
0L
0L
0
–A
0
L
L
0L
0L
1L
L
–A
–A
L
–I/O
L
L
L
15
–I/O
[2]
[2]
L
15/16L
15/16L
for 64K devices; A
7
[3]
for x8 devices; I/O
7/8L
[1]
CC
SB3
= 115 mA (typical)
CE
= 10 µA (typical)
16/17
0
L
8/9
–A
0
–I/O
16
for 128K.
8
for x9 devices.
Address
Decode
16/17
198 Champion Court
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
Master/Slave chip select when using more than one
device
between ports
Pb-Free packages available
Control
I/O
San Jose
Dual-Port Static RAM
Address
,
Decode
3.3V 64K/128K x 8/9
CA 95134-1709
16/17
Revised September 6, 2005
16/17
CY7C008V/009V
CY7C018V/019V
8/9
CE
R
I/O
A
A
408-943-2600
[3]
0R
0R
0R
–A
–A
–I/O
[2]
[2]
BUSY
SEM
R/W
15/16R
15/16R
CE
CE
R/W
[1]
INT
OE
OE
CE
7/8R
0R
1R
R
R
R
R
R
R
R
R
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Related parts for CY7C019V-20AC

CY7C019V-20AC Summary of contents

Page 1

... CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • ...

Page 2

Functional Description The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided ...

Page 3

... Typical Standby Current for I SB1 (Both ports TTL level) Typical Standby Current for I SB3 (Both ports CMOS level) Note: 5. This pin is NC for CY7C018V. Document #: 38-06044 Rev. *C 100-Pin TQFP (Top View CY7C019V (128K x 9) CY7C018V (64K CY7C008V/009V CY7C008V/009V CY7C018V/019V CY7C018V/019V -15 - 125 ...

Page 4

... Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State............................–0. Notes: 6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 7. Industrial parts are available in CY7C009V and CY7C019V only. Document #: 38-06044 Rev. *C Description Chip Enable (CE is LOW when CE Read/Write Enable ...

Page 5

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( Output LOW Voltage ( Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current IX I Output Leakage ...

Page 6

Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [11 LOW to Data Valid ACE t OE LOW to ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description t R/W HIGH after BUSY HIGH (Slave) WH [17] t BUSY HIGH to Data Valid BDD [16] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t ...

Page 8

Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access DATA OUT CURRENT I SB [19, 21, 22, 23] ...

Page 9

Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [28 R/W NOTE 30 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [28 R/W DATA IN Notes: 24. ...

Page 10

Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...

Page 11

Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW. ...

Page 12

Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...

Page 13

Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009V/19V R/W L INT R [39] t INS Right Side Clears INT : R ADDRESS R/W R ...

Page 14

Architecture The CY7C008V/009V and CY7018V/019V consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access ...

Page 15

If both ports attempt to access the semaphore within t of each other, the semaphore will SPS Table 1. Non-Contending Read/Write Inputs CE R/W OE ...

Page 16

... CY7C009V-20AC CY7C009V-20AI CY7C009V-20AXI 25 CY7C009V-25AC CY7C009V-25AXC 128K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C019V-15AC CY7C019V-15AXC 20 CY7C019V-20AC CY7C019V-20AXC CY7C019V-20AI CY7C019V-20AXI 25 CY7C019V-25AC CY7C019V-25AXC Document #: 38-06044 Rev. *C Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 ...

Page 17

... Document #: 38-06044 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 18

... Document #: 38-06044 Rev. *C Description of Change Change from Spec number: 38-00669 to 38-06044 Change pin 85 from BUSYL to BUSYR (pg. 3) Power up requirements added to Maximum Ratings Information Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI, CY7C019V-25AXC CY7C008V/009V CY7C018V/019V Page [+] Feedback ...

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