CY7C038V-25AC Cypress Semiconductor Corp, CY7C038V-25AC Datasheet

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CY7C038V-25AC

Manufacturer Part Number
CY7C038V-25AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C038V-25AC

Density
1.125Mb
Access Time (max)
25ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
165mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
18b
Number Of Words
64K
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C038V-25AC
Manufacturer:
TI
Quantity:
4 813
Features
Notes
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *B
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.
2. CY7C037V and CY7C037AV are functionally identical.
3. I/O
4. I/O
5. A
6. BUSY is an output in master mode and an input in slave mode.
True Dual-Ported memory cells which allow
simultaneous access of the same memory location
32K x 16 organization (CY7C027V/027VN/027AV
64K x 16 organization (CY7C028V)
32K x 18 organization (CY7C037V/037AV
64K x 18 organization (CY7C038V)
0.35 micron CMOS for optimum speed and power
High speed access: 15, 20, and 25 ns
Low operating power
Active: I
Standby: I
Logic Block Diagram
0
–A
8
0
–I/O
–I/O
14
for 32K; A
CC
15
7
R/W
UB
CE
CE
OE
I/O
I/O
A
A
CE
OE
R/W
SEM
BUSY
INT
UB
LB
LB
for x16 devices; I/O
0L
0L
SB3
for x16 devices; I/O
L
= 115 mA (typical)
L
0L
1L
8/9L
0L
L
L
L
L
L
–A
–A
L
L
L
–I/O
L
[5]
[5]
L
= 10 μA (typical)
14/15L
14/15L
–I/O
[6]
0
–A
[4]
7/8L
[3]
15/17L
15
for 64K devices.
CE
0
9
–I/O
–I/O
15/16
L
8/9
8/9
8
17
for x18 devices.
for x18 devices.
Address
Decode
15/16
[2]
)
198 Champion Court
Control
[1]
3.3V 32K/64K x 16/18 Dual-Port Static
I/O
)
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
Control
Fully asynchronous operation
Automatic power down
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Dual chip enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
100-pin Pb-free TQFP and 100-pin TQFP
I/O
San Jose
CY7C027V/027VN/027AV/028V
Address
Decode
15/16
,
CA 95134-1709
CY7C037V/037AV/038V
15/16
8/9
8/9
CE
R
I/O
Revised December 09, 2008
8/9L
I/O
A
A
[6]
0R
0R
–I/O
0L
–A
–A
–I/O
[5]
[5]
BUSY
SEM
R/W
15/17R
14/15R
14/15R
CE
CE
R/W
[3]
INT
UB
LB
OE
OE
CE
UB
[4]
LB
7/8R
0R
1R
R
R
R
R
R
R
R
R
R
R
R
R
408-943-2600
RAM
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CY7C038V-25AC Summary of contents

Page 1

... CMOS for optimum speed and power ■ High speed access: 15, 20, and 25 ns ■ Low operating power ■ ...

Page 2

Pin Configurations 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [1] A15L LBL 10 UBL 11 CE0L 12 CE1L 13 CY7C027V/027VN/027AV (32K x 16) SEML 14 VCC ...

Page 3

... TTL level) SB1 Typical Standby Current for I (Both ports CMOS level) SB3 Note 2. This pin is NC for CY7C037V/037AV. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Figure 2. 100-Pin TQFP (Top View CY7C038V (64K x 18) CY7C037V/037AV (32K x 18 -15 15 125 35 10 μA CY7C037V/037AV/038V 80 79 ...

Page 4

Pin Definitions Left Port Right Port R/W R –A A –A 0L 15L 0R 15R I/O –I/O I/O –I/O 0L 17L 0R 17R ...

Page 5

The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy ...

Page 6

... Input Capacitance IN C Output Capacitance OUT Notes 2. Pulse width < 20 ns. 3. Industrial parts are available in CY7C028V and CY7C038V only 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level standby I MAX ...

Page 7

R1 = 590Ω OUTPUT 435Ω (a) Normal Load (Load 1) 3.0V GND Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA ...

Page 8

Switching Characteristics Over the Operating Range Parameter Description t Data Hold From Write End HD [9, 10] t R/W LOW to High Z HZWE [9 ,10] t R/W HIGH to Low Z LZWE [36] t Write Pulse to Data Delay ...

Page 9

Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...

Page 10

Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [24,25 R/W NOTE 27 DATA OUT DATA IN Figure 8. Write Cycle No Controlled Timing ADDRESS [24,25 R/W ...

Page 11

Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Figure 10. Timing Diagram of Semaphore Contention A – R/W L ...

Page 12

Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 33. CE ...

Page 13

Switching Waveforms (continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Figure 14. Busy Timing ...

Page 14

Switching Waveforms (continued) Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R [36] t INS Right Side Clears INT : R ADDRESS R INT ...

Page 15

Table 1. Non-Contending Read/Write Inputs CE R ...

Page 16

... Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C038V-15AC CY7C038V-15AXC 20 CY7C038V-20AC CY7C038V-20AXC CY7C038V-20AI CY7C038V-20AXI 25 CY7C038V-25AC CY7C038V-25AXC Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb-Free Thin Quad Flat Pack A100 100-Pin Pb-Free Thin Quad Flat Pack ...

Page 17

Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V 51-85048-*C Page [+] Feedback ...

Page 18

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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