GS816036BGT-150I GSI TECHNOLOGY, GS816036BGT-150I Datasheet

GS816036BGT-150I

Manufacturer Part Number

GS816036BGT-150I

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS816036BGT-150I.pdf (23 pages)

Specifications of GS816036BGT-150I

Density

18Mb

Access Time (max)

7.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

133.3MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

19b

Package Type

TQFP

Operating Temp Range

-40C to 85C

Number Of Ports

Supply Current

200mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

512K

Lead Free Status / RoHS Status

Compliant

Current page: 1 of 23
Download datasheet (753Kb)

100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Rev: 1.05 9/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Flow Through

Pipeline

3-1-1-1

2-1-1-1

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/23

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS816018/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

-250

295

345

225

255

2.5

4.0

5.5

-200

245

285

200

220

3.0

5.0

6.5

DDQ

GS816018/32/36BT-250/200/150

) pins are used to decouple output noise

-150

200

225

185

205

3.8

6.7

7.5

Unit

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS816036BGT-150I

GS816036BGT-150I Summary of contents

Page 1

... Curr (x18) 255 220 Curr (x32/x36) 1/23 GS816018/32/36BT-250/200/150 250 MHz–150 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ -150 Unit 3.8 ns 6.7 ns 200 mA 225 mA 7.5 ns 7.5 ns 185 mA 205 mA © 2004, GSI Technology DD ...

Page 2

... Pins marked with NC can be tied to either V Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816018B 100-Pin TQFP Pinout Top View These pins can also be left floating 2/23 GS816018/32/36BT-250/200/150 DDQ DQP DDQ DDQ DDQ © 2004, GSI Technology ...

Page 3

... Pins marked with NC can be tied to either V Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816032B 100-Pin TQFP Pinout 512K x 32 Top View These pins can also be left floating 3/23 GS816018/32/36BT-250/200/150 DDQ DDQ DDQ DDQ © 2004, GSI Technology ...

Page 4

... Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816036B 100-Pin TQFP Pinout 512K x 36 Top View These pins can also be left floating 4/23 GS816018/32/36BT-250/200/150 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2004, GSI Technology ...

Page 5

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/23 © 2004, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816018/32/36B Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/23 GS816018/32/36BT-250/200/150 A Memory Array – DQx1 DQx9 © 2004, GSI Technology ...

Page 7

... C D Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com may be used in any combination with BW to write single or multiple bytes. D 7/23 GS816018/32/36BT-250/200/150 B B Notes and/ © 2004, GSI Technology ...

Page 8

... Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. State Diagram ADSP ADSC Key 8/23 GS816018/32/36BT-250/200/150 ADV High High High High High © 2004, GSI Technology ...

Page 9

... ADSP is tied high and ADV is tied low. Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 9/23 GS816018/32/36BT-250/200/150 First Read Burst Read BW, and GW © 2004, GSI Technology ...

Page 10

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 10/23 GS816018/32/36BT-250/200/150 First Read Burst Read CR © 2004, GSI Technology ...

Page 11

... V maximum, with a pulse width not to exceed 50% tKC. DDn 11/23 GS816018/32/36BT-250/200/150 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 DDQ –0 +0.5 DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 12

... Min. Typ – +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 12/23 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2004, GSI Technology ...

Page 13

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 13/23 GS816018/32/36BT-250/200/150 50% tKC DD IL Typ. Max. Unit 30pF © 2004, GSI Technology ...

Page 14

... IN I Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 14/23 GS816018/32/36BT-250/200/150 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 2004, GSI Technology Max — — 0.4 V ...

Page 15

... GS816018/32/36BT-250/200/150 -250 -200 -150 –40 0 – 85°C 70°C 85°C 70°C 315 255 265 205 245 205 215 190 285 230 240 185 225 190 200 175 © 2004, GSI Technology –40 Unit to 85°C 215 mA 20 200 mA 15 195 mA 15 185 ...

Page 16

... GSI Technology ...

Page 17

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 17/23 GS816018/32/36BT-250/200/150 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology Deselect tKQX tHZ ...

Page 18

... Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 18/23 GS816018/32/36BT-250/200/150 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2004, GSI Technology tKQX ...

Page 19

... Rev: 1.05 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 19/23 GS816018/32/36BT-250/200/150 2. The duration of SB tZZR © 2004, GSI Technology ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 20/23 GS816018/32/36BT-250/200/150 E1 E © 2004, GSI Technology ...

Page 21

... GS816032BGT-200 512K x 32 GS816032BGT-150 512K x 36 GS816036BGT-250 512K x 36 GS816036BGT-200 512K x 36 GS816036BGT-150 GS816018BGT-250I GS816018BGT-200I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 22

... GS816036BGT-250I 512K x 36 GS816036BGT-200I 512K x 36 GS816036BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 23

... Added 300 MHz speed bin Content • Removed 300 MHz speed bin Content • Added Status column to Ordering Information table • Changed Pb-free to RoHS-compliant • Updated Truth Tables (pg. 7,8) Content • Updated for MP status Content 23/23 GS816018/32/36BT-250/200/150 Page;Revisions;Reason © 2004, GSI Technology ...

Related keywords

GS816036BGT-150I datasheet
GS816036BGT-150I data sheet
GS816036BGT-150I pdf datasheet
GS816036BGT-150I component
GS816036BGT-150I part
GS816036BGT-150I distributor
GS816036BGT-150I RoHS
GS816036BGT-150I datasheet download