ISP1760ET STEricsson, ISP1760ET Datasheet
ISP1760ET
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ISP1760ET Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications Rev. 04 — 4 February 2008 1. General description The ISP1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic processor interface. It integrates one Enhanced Host ...
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NXP Semiconductors I Generic processor interface, non-multiplexed and variable latency, with a configurable 32-bit or 16-bit external data bus; the processor interface can be defined as variable-latency or SRAM type (memory mapping) I Slave DMA support to reduce the load ...
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... Type number Package Name Description ISP1760BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 ISP1760ET TFBGA128 plastic thin fine-pitch ball grid array package; 128 balls; body 9 ISP1760_4 Product data sheet Embedded Hi-Speed USB host controller Rev. 04 — 4 February 2008 ...
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NXP Semiconductors 5. Block diagram 47, 49, 51, 52 78, 80 DATA[15:0]/DATA[31:0] 82, 84, ...
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... Product data sheet 1 ISP1760BE 38 Pin configuration (LQFP128); top view ball A1 index area Pin configuration (TFBGA128); top view Rev. 04 — 4 February 2008 Embedded Hi-Speed USB host controller 102 65 004aaa505 ISP1760ET 004aaa550 © NXP B.V. 2008. All rights reserved. ISP1760 5 of 110 ...
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NXP Semiconductors 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin LQFP128 TFBGA128 OC3_N 1 C2 REF5V 2 A2 TEST1 3 B2 GNDA 4 A1 REG1V8 CC(5V0 CC(5V0) GND(OSC ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 PSW2_N 28 M1 GND(RREF3 RREF3 30 N1 [6] GNDA 31 P2 DM3 32 P1 GNDA 33 R2 DP3 34 R1 PSW3_N 35 T1 GNDD 36 T2 ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA9 49 T8 REG1V8 50 R8 DATA10 51 P9 DATA11 52 T9 GNDC 53 R9 DATA12 54 T10 GNDD 55 R10 DATA13 56 P11 DATA14 57 T11 DATA15 ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA21 66 R15 V 67 P15 CC(I/O) DATA22 68 T16 DATA23 69 R16 DATA24 70 P16 GNDD 71 N16 DATA25 72 N15 DATA26 73 M15 DATA27 74 M16 ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 A2 84 H15 REG1V8 85 G16 A3 86 H14 A4 87 F16 GNDC 88 G15 A5 89 F15 GNDD 90 E16 A6 91 F14 A7 92 E15 A8 ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 CS_N 106 A12 RD_N 107 B12 WR_N 108 B11 GNDD 109 A11 BAT_ON_N 110 C10 n.c. 111 A10 IRQ 112 B10 n.c. 113 A9 DREQ 114 B9 V ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 TEST7 126 A4 OC1_N 127 B3 OC2_N 128 A3 [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. [2] All ground pins should ...
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NXP Semiconductors 7. Functional description 7.1 ISP1760 internal architecture: advanced NXP slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced NXP slave host controller. The EHCI is the ...
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NXP Semiconductors Fig 4. 7.1.1 Internal clock scheme and port selection The ISP1760 has three ports. Fig 5. Figure 5 enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by external ...
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NXP Semiconductors Table 3. Port connection scenarios Port configuration Port 1 One port (port 1) DP and DM are routed to USB connector One port (port 2) DP and DM are not connected (left open) One port (port 3) DP ...
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NXP Semiconductors A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on ...
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NXP Semiconductors • The address range of the internal RAM buffer is from 0400h to FFFFh. • The internal memory contains isochronous, interrupt and asynchronous PTDs, and respective defined payloads. • All accesses to the internal memory are double word ...
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NXP Semiconductors Both the CPU interface logic and the USB host controller require access to the internal ISP1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus ...
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NXP Semiconductors Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch data. That is, the fetching of data is independent of the address on A[15:0] lines. ...
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NXP Semiconductors The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1760 memory address. A register or memory access or access to other system memory can occur in between ...
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NXP Semiconductors – Enable ENABLE_DMA (bit 1) of the DMA Configuration register to determine the assertion of DREQ immediately after setting the bit. After programming the preceding parameters, the system’s DMA may be enabled, waiting for the DREQ to start ...
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NXP Semiconductors • event of interrupt occurs but the respective bit in the Interrupt Enable register is not set, then the respective Interrupt register bit is set but the interrupt signal is not asserted. An interrupt will be ...
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NXP Semiconductors Table 5. PTD 7.5 Phase-Locked Loop (PLL) clock multiplier The internal PLL requires a 12 MHz input, which can MHz crystal MHz clock ...
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NXP Semiconductors The SUSPEND/WAKEUP_N pin is a 3-state output also an input to the internal wake-up logic. When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of the SUSPEND/WAKEUP_N pin: • remains ...
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NXP Semiconductors 7.7 Overcurrent detection The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit ...
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NXP Semiconductors 7.8 Power supply Figure 8 Fig 8. Figure 9 Fig 9. 7.8.1 Hybrid mode Table 6 ISP1760_4 Product data sheet shows the ISP1760 power supply connection. ISP1760BE V CC(5V0 10, 40, 48, V CC(I/O) 59, 67, ...
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NXP Semiconductors Table 6. Voltage V CC(5V0) V CC(I/O) In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current CC(5V0) back on, before the resume programming ...
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NXP Semiconductors To give a better view of the functionality, dips and t4 to t5. If the dip too short, that is, < the internal POR pulse will not ...
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NXP Semiconductors 8. Registers Table 8 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent accesses ...
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NXP Semiconductors Table 8. Address 0344h 0354h 0374h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. CAPLENGTH ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol PRR Reset 0 Access R Table 12. Bit ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 1 Access R Table 14. Bit [1] ...
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NXP Semiconductors Table 15. USBCMD - USB Command register (address 0020h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 18. ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol reserved Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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NXP Semiconductors Table 22. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2.6 PORTSC1 register The Port Status and Control (PORTSC) register (bit allocation: well reset by hardware ...
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NXP Semiconductors Table 24. Bit [1] For details on register bit description, refer to Universal Serial ...
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NXP Semiconductors Table 26. ISO PTD Skip Map register (address 0134h) bit description Bit Symbol Access ISO_PTD_SKIP R/W _MAP[31:0] When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped ...
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NXP Semiconductors When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not ...
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NXP Semiconductors 8.2.15 ATL PTD Last PTD register The bit description of the ATL PTD Last PTD register is given in Table 33. ATL PTD Last PTD register (address 0158h) bit description Bit Symbol Access Value ATL_PTD_LAST ...
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NXP Semiconductors Table 35. Bit 8.3.2 Chip ID register Read this register to get the ID of the ISP1760. The upper word ...
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NXP Semiconductors Table 36. Chip ID - Chip Identifier register (address 0304h) bit description Bit Symbol Access Value CHIPID[31:0] R 8.3.3 Scratch register This register is for testing and debugging purposes only. The value read back must ...
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NXP Semiconductors Table 39. Bit 8.3.5 DMA Configuration register The bit allocation of the DMA Configuration register is given in Table 40. DMA Configuration register (address 0330h) bit allocation Bit 31 Symbol Reset 0 Access ...
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NXP Semiconductors Table 41. Bit 8.3.6 Buffer Status register The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is, ATL, INT and ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 43. Bit 8.3.7 ATL Done Timeout register The bit description ...
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NXP Semiconductors Table 45. Memory register (address 033Ch) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access ...
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NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 48. Bit ...
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NXP Semiconductors Table 50. Bit 8.3.11 Power Down Control register This register is used to turn off power to the internal blocks of the ISP1760 to obtain maximum power savings. Table 51. Power Down ...
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NXP Semiconductors Table 52. [1] Bit CLK_OFF_ ISP1760_4 Product data sheet Power Down Control register (address 0354h) bit description Symbol Description Clock Off Counter: ...
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NXP Semiconductors Table 52. [1] Bit [1] For a 32-bit operation, the default wake-up counter value For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write ...
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NXP Semiconductors Table 54. [1] Bit [1] For correct port 1 initialization, write 0080 0018h to this register after power-on. 8.4 Interrupt ...
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NXP Semiconductors Table 56. Bit ISP1760_4 Product data sheet Interrupt register (address 0310h) bit description Symbol Description reserved; write reset value ISO_IRQ ISO IRQ: Indicates that an ISO PTD ...
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NXP Semiconductors Table 56. Bit 8.4.2 Interrupt Enable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 57. Interrupt Enable register (address 0314h) bit allocation Bit 31 ...
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NXP Semiconductors Table 58. Bit 8.4.3 ISO IRQ Mask OR register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is ...
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NXP Semiconductors Table 59. ISO IRQ Mask OR register (address 0318h) bit description Bit Symbol Access ISO_IRQ_MASK R/W _OR[31:0] 8.4.4 INT IRQ Mask OR register Each bit of this register (see and is a hardware IRQ mask ...
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NXP Semiconductors Table 63. INT IRQ Mask AND register (address 0328h) bit description Bit Symbol Access INT_IRQ_MASK R/W _AND[31:0] 8.4.8 ATL IRQ Mask AND register Each bit of this register corresponds to one of the 32 ATL ...
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NXP Semiconductors Multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by endpoint data structures, until it reaches the end of the endpoint list. There are three endpoint lists: one for ...
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NXP Semiconductors Fig 13. NextPTD traversal rule ISP1760_4 Product data sheet START PTD SCHEDULE no PTD SKIPPED? CHECK FOR yes VALID AND ACTIVE BIT SET? START PTD no EXECUTION FOLLOW NEXT PTD POINTED BY NEXTPTD POINTER Rev. 04 — 4 ...
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High-speed bulk IN and OUT Table 65 shows the bit allocation of the high-speed bulk IN and OUT, bulk Transfer Descriptor. Table 65. High-speed bulk IN and OUT: bit allocation Bit ...
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NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - 5 J ...
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NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access Cerr[1:0] HW — writes SW — writes NakCnt[3:0] HW — writes SW — writes reserved - 46 ...
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NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW ...
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High-speed isochronous IN and OUT Table 67 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD). Table 67. High-speed isochronous IN and OUT: bit allocation Bit ...
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NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ...
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NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access — sets — writes — writes reserved - NrBytes HW — ...
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NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access NrBytesTo SW — writes Transfer[14: reserved - — resets SW — sets ISP1760_4 Product data sheet Embedded ...
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High-speed interrupt IN and OUT Table 69 shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD). Table 69. High-speed interrupt IN and OUT: bit allocation Bit ...
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NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 ...
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NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — ...
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NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: ...
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Start and complete split for bulk Table 72 shows the bit allocation of Start Split (SS) and Complete Split (CS) for bulk, asynchronous Start Split and Complete Split (SS/CS) Transfer Descriptor (TD). Table 72. Start and complete split for ...
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NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - 5 ...
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NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol Access NrBytesTransferred HW — writes [14:0] DW2 reserved - RL[3:0] SW — writes 24 reserved - 23 ...
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NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol Access NrBytesToTransfer SW — writes [14: reserved - — sets HW — resets Table 74. Bulk I/O ...
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Start and complete split for isochronous Table 75 shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD). Table 75. Start and complete split for isochronous: bit allocation Bit ...
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NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] ...
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NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 — sets HW — resets 62 H ...
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NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] ...
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Start and complete split for interrupt Table 77 shows the bit allocation of start and complete split for interrupt. Table 77. Start and complete split for interrupt: bit allocation Bit ...
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NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] ...
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NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access Status0[2:0] HW — writes SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 ...
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NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access PortNumber[6:0] SW — writes SE[1:0] SW — writes 47 reserved - — writes ...
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NXP Semiconductors Table 80. Interrupt I/O I/O ISP1760_4 Product data sheet SE description Rev. 04 — 4 February 2008 ISP1760 Embedded Hi-Speed USB host controller E Remarks 0 low-speed 0 full-speed © NXP B.V. 2008. All rights ...
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NXP Semiconductors 10. Power consumption Table 81. Number of ports working One port working (high-speed Two ...
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NXP Semiconductors 11. Limiting values Table 82. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage (5.0 V) CC(5V0) I latch-up current lu V electrostatic discharge voltage ...
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NXP Semiconductors 13. Static characteristics Table 84. Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; T Symbol Parameter ...
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NXP Semiconductors Table 86. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter V high-speed ...
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NXP Semiconductors 14. Dynamic characteristics Table 88. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External ...
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NXP Semiconductors Table 91. Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Driver characteristics t rise time FR t fall time ...
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NXP Semiconductors 14.1 PIO timing 14.1.1 Register or memory write Fig 15. Register or memory write Table 93 +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t h11 ...
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NXP Semiconductors 14.1.2 Register read Fig 16. Register read Table 94 +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t ...
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NXP Semiconductors Table 95 +85 C; unless otherwise specified. amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 14.1.4 Memory read A[17:1] DATA CS_N ...
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NXP Semiconductors Table 96 +85 C; unless otherwise specified. amb Symbol t d23 t w13 t su13 t su23 14.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity ...
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NXP Semiconductors Table 97 +85 C; unless otherwise specified. amb Symbol t w14 t a34 t a44 t h14 14.2.2 Single cycle: DMA write Fig 20. DMA write (single cycle) Table 98 ...
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NXP Semiconductors 14.2.3 Multi-cycle: DMA read Fig 21. DMA read (multi-cycle burst) Table 99 +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) t a16 t a26 t ...
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NXP Semiconductors 14.2.4 Multi-cycle: DMA write Fig 22. DMA write (multi-cycle burst) Table 100. DMA write (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) T ...
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NXP Semiconductors 15. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT A A ...
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NXP Semiconductors TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 0.8 mm ball A1 index area ball ...
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NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction ...
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NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Soldering of through-hole mount packages 17.1 Introduction to soldering through-hole mount ...
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NXP Semiconductors 17.4 Package related soldering information Table 103. Suitability of through-hole mount IC packages for dipping and wave soldering Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be ...
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NXP Semiconductors Table 104. Abbreviations Acronym OC OHCI PCI PDA PID PIO PLL PMOS POR PORP PTD RISC SE0 SE1 siTD SOF SRP SS TT UHCI USB 19. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller ...
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NXP Semiconductors 20. Revision history Table 105. Revision history Document ID Release date ISP1760_4 20080204 • Modifications: Section 7.3 “Accessing the ISP1760 host controller memory: PIO and paragraph. • Table 52 “Power Down Control register (address 0354h) bit bits 12 ...
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NXP Semiconductors 21. Legal information 21.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Table 57. Interrupt Enable register (address 0314h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ...
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NXP Semiconductors 24. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
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NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 17.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . 101 17.4 Package related soldering information . . . . . 102 18 Abbreviations ...