FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet
FW82801DBM S L6DN
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... Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet January 2003 Order Number: 252337-001 ...
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... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries ...
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... ACPI 2.0 compliant — ACPI-defined power states (C1–C4, S1-M, S3–S5) — ACPI power management timer ® TM — Support for “Intel SpeedStep technology” processor power control — (Support for “Deeper Sleep” power state — PCI CLKRUN# and PME# support — ...
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... LPC Interface Firmware Hubs (1-8) Super I/O Super I/O Othe ASIC Other ASICs r s (Optional) Memory Power Management Clock Generators Clock Generators System Management (TCO) SMBus PCI Bus Docking Bridge Cardbus Controller (and Attached Slots) SysBlk_ICH4-M ® Intel 82801DBM ICH4-M Datasheet ...
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... Functional Description 5.1 Hub Interface to PCI Bridge (D30:F0)............................................................ 73 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 ® Intel 82801DBM ICH4-M Datasheet ...........................................................................................................33 ..............................................................................................43 2.20.4.1 Test Mode Selection.......................................................... 62 .....................................................................................73 PCI Bus Interface.............................................................................. 73 PCI-to-PCI Bridge Model .................................................................. 74 IDSEL to Device Number Mapping ................................................... 74 SERR# Functionality......................................................................... 74 Parity Error Detection........................................................................ 76 Standard PCI Bus Configuration Mechanism ................................... 77 ...
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... Address Shifting When Programmed for 16-Bit I/O Count by Words ......................................................................... 100 Autoinitialize.................................................................................... 100 Software Commands ...................................................................... 101 5.4.5.1 Clear Byte Pointer Flip-Flop ............................................ 101 5.4.5.2 DMA Master Clear........................................................... 101 5.4.5.3 Clear Mask Register........................................................ 101 PCI DMA Expansion Protocol ......................................................... 102 ® Intel 82801DBM ICH4-M Datasheet ...
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... Advanced Interrupt Controller (APIC) (D31:F0) ...........................................119 5.8.1 5.8.2 5.8.3 5.8.4 ® Intel 82801DBM ICH4-M Datasheet PCI DMA Expansion Cycles ...........................................................103 DMA Addresses ..............................................................................104 DMA Data Generation.....................................................................104 DMA Byte Enable Generation.........................................................104 DMA Cycle Termination ..................................................................105 LPC DMA ........................................................................................105 Asserting DMA Requests ...
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... Processor Interface (D31:F0) ...................................................................... 136 5.11.1 Processor Interface Signals ............................................................ 136 5.11.2 Speed Strapping for Processor....................................................... 139 5.12 Power Management (D31:F0) ..................................................................... 140 5.12.1 Intel 5.12.2 System Power Planes..................................................................... 143 5.12.3 Intel 5.12.4 SMI#/SCI Generation...................................................................... 143 5.12.5 Dynamic Processor Clock Control .................................................. 145 5.12.6 Dynamic PCI Clock Control ............................................................ 148 5 ...
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... SpeedStep Technology Protocol ........................................155 5.12.9.1 Intel SpeedStep Technology Processor Requirements...156 5.12.9.2 Intel SpeedStep Technology States ................................156 5.12.9.3 Voltage Regulator Interface.............................................156 5.12.10.1 PWRBTN# - Power Button ..............................................157 5.12.10.2 Ring Indicate (RI#)...........................................................158 5.12.10.3 PCI Power Management Event (PME#) ..........................158 5.12.10.4 SYS_RESET# Signal ......................................................158 5 ...
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... Data Packets ................................................................... 202 5.16.5.4 Handshake Packets ........................................................ 202 5.16.5.5 Handshake Responses ................................................... 203 5.16.6.1 Transaction Based Interrupts .......................................... 203 5.16.6.2 Non-Transaction Based Interrupts .................................. 205 5.17.1.1 Power On ........................................................................ 209 5.17.1.2 BIOS Initialization ............................................................ 209 5.17.1.3 Driver Initialization ........................................................... 210 5.17.1.4 EHC Resets..................................................................... 210 ® Intel 82801DBM ICH4-M Datasheet ...
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... AC ’97 Controller Functional Description (Audio D31:F5, Modem D31:F6).242 5.19.1 PCI Power Management.................................................................244 5.19.2 AC-Link Overview ...........................................................................245 ® Intel 82801DBM ICH4-M Datasheet 5.17.3.1 Periodic List Execution ....................................................211 5.17.3.2 Asynchronous List Execution ..........................................212 5.17.6.1 Aborts on USB EHCI-Initiated Memory Reads ................214 5 ...
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... BCC—Base-Class Code Register (LAN Controller—B1:D8:F0)..... 269 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ....... 269 PMLT—PCI Master Latency Timer Register (LAN Controller—B1:D8:F0) ........................................................... 270 Register (LAN Controller—B1:D8:F0)............................................. 270 (LAN Controller—B1:D8:F0) ........................................................... 271 ....................................................... 265 ® Intel 82801DBM ICH4-M Datasheet ...
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... IOLIM—I/O Limit Register (HUB-PCI—D30:F0) .............................295 8.1.16 SECSTS—Secondary Status Register (HUB-PCI—D30:F0)..........296 8.1.17 MEMBASE—Memory Base Register (HUB-PCI—D30:F0) ............297 ® Intel 82801DBM ICH4-M Datasheet (LAN Controller—B1:D8:F0) ...........................................................272 (LAN Controller—B1:D8:F0) ...........................................................273 (LAN Controller—B1:D8:F0) ...........................................................274 (LAN Controller— ...
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... SCC—Sub-Class Code Register (LPC I/F—D31:F0) ..................... 309 BCC—Base-Class Code Register (LPC I/F—D31:F0) ................... 309 HEADTYP—Header Type Register (LPC I/F—D31:F0) ................. 309 (LPC I/F—D31:F0) .......................................................................... 312 (LPC I/F—D31:F0) .......................................................................... 313 (LPC I/F—D31:F0) .......................................................................... 314 (LPC I/F—D31:F0) .......................................................................... 314 ................................................ 305 ® Intel 82801DBM ICH4-M Datasheet ...
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... ELCR2—Slave Controller Edge/Level Triggered Register .............346 9.5 Advanced Interrupt Controller (APIC) ..........................................................347 9.5.1 9.5.2 ® Intel 82801DBM ICH4-M Datasheet (LPC I/F—D31:F0) ..........................................................................319 (LPC I/F—D31:F0) ..........................................................................320 (LPC I/F—D31:F0) ..........................................................................321 (LPC I/F—D31:F0) ..........................................................................321 (LPC I/F—D31:F0) ..........................................................................322 (LPC I/F— ...
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... PM1_CNT—Power Management 1 Control Register...... 373 9.8.3.4 PM1_TMR—Power Management 1 Timer Register ........ 374 9.8.3.5 PROC_CNT—Processor Control Register...................... 374 9.8.3.6 LV2 — Level 2 Register .................................................. 375 9.8.3.7 LV3—Level 3 Register .................................................... 376 9.8.3.8 LV4—Level 4 Register .................................................... 376 9.8.3.9 PM2_CNT—Power Management 2 Control .................... 376 ® Intel 82801DBM ICH4-M Datasheet ...
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... DEVTRAP_EN— Device Trap Enable Register ..............386 9.8.3.19 BUS_ADDR_TRACK— Bus Address Tracker.................387 9.8.3.20 BUS_CYC_TRACK— Bus Cycle Tracker .......................387 ® 9.8.3.21 SS_CNT— Intel SpeedStep TCO_RLD—TCO Timer Reload and Current Value Register .........389 TCO_TMR—TCO Timer Initial Value Register ...............................390 TCO_DAT_IN— ...
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... PORTSC[0,1]—Port Status and Control Register........................... 435 18 (IDE D31:F1)................................................................................... 406 (IDE—D31:F1) ................................................................................ 406 (IDE—D31:F1) ................................................................................ 410 (IDE—D31:F1) ................................................................................ 411 (IDE—D31:F1) ................................................................................ 412 (IDE—D31:F1) ................................................................................ 413 ................................................................ 419 (USB—D29:F0/F1/F2) .................................................................... 424 (USB—D29:F0/F1/F2) .................................................................... 425 (USB—D29:F0/F1/F2) .................................................................... 426 ® Intel 82801DBM ICH4-M Datasheet ...
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... PWAKE_CAP—Port Wake Capability Register 12.1.26 PORT_OVRIDE—USB UHCI Port Override Register 12.1.27 LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability 12.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / 12.1.29 SPECIAL_SMI—Intel Specific USB EHCI SMI Register 12.1.30 ACCESS_CNTL—Access Control Register ® Intel 82801DBM ICH4-M Datasheet ...
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... CONFIGFLAG—Configure Flag Register ....................... 464 12.2.2.9 PORTSC—Port N Status and Control Register .............. 465 12.2.3.1 Control/Status Register ................................................... 468 12.2.3.2 USB PIDs Register.......................................................... 470 12.2.3.3 Data Buffer Bytes 7:0 Register........................................ 470 12.2.3.4 Configuration Register..................................................... 471 (SMBUS—D31:F3)476 ...................................................... 473 ® Intel 82801DBM ICH4-M Datasheet ...
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... Valid Index Register ...................................................505 14.2.4 x_SR—Status Register ...................................................................506 14.2.5 x_PICB—Position In Current Buffer Register .................................507 14.2.6 x_PIV—Prefetched Index Value Register .......................................507 ® Intel 82801DBM ICH4-M Datasheet (Audio—D31:F5) .............................................................................494 (Audio—D31:F5) .............................................................................495 (Audio—D31:F5) .............................................................................496 (Audio—D31:F5) .............................................................................499 (Audio— ...
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... Electrical Characteristics 17.1 Absolute Maximum Ratings ......................................................................... 541 17.2 Functional Operating Range ........................................................................ 541 17.3 DC Characteristics ....................................................................................... 542 17.4 AC Characteristics ....................................................................................... 548 17.5 Timing Diagrams.......................................................................................... 565 22 (Modem—D31:F6) .......................................................................... 519 (Modem—D31:F6) .......................................................................... 521 (Modem—D31:F6) .......................................................................... 522 (Modem—D31:F6) .......................................................................... 522 .............................................................................................. 533 .............................................................................. 541 ....................................... 515 ® Intel 82801DBM ICH4-M Datasheet ...
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... Package Information 19 Testability 19.1 Test Mode Description .................................................................................579 19.2 Tri-State Mode .............................................................................................580 19.3 XOR Chain Mode.........................................................................................580 19.3.1 XOR Chain Testability Algorithm Example .....................................580 A Register Index B Register Bit Index ® Intel 82801DBM ICH4-M Datasheet .......................................................................................577 .............................................................................................................579 .............................................................................................589 ........................................................................................607 23 ...
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... AC ’97 2.3 Controller-Codec Connection..................................................... 245 5-23 AC-Link Protocol.......................................................................................... 246 5-24 AC-Link Powerdown Timing ........................................................................ 253 5-25 SDIN Wake Signaling .................................................................................. 254 16-1 Intel 16-2 Intel 17-1 Clock Timing ................................................................................................ 565 17-2 Valid Delay from Rising Clock Edge ............................................................ 565 17-3 Setup and Hold Times ................................................................................. 565 17-4 Float Delay ...
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... Intel 18-2 Intel 19-1 Test Mode Entry (XOR Chain Example) ......................................................579 19-2 Example XOR Chain Circuitry......................................................................580 ® Intel 82801DBM ICH4-M Datasheet ® ® Speedstep Technology Timing Sequence .......................................576 ® ICH4-M Package (Top and Side Views) ............................................577 ® ICH4-M Package (Bottom View) ........................................................578 ...
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... Content of Interrupt Vector Byte .................................................................. 113 5-17 APIC Interrupt Mapping ............................................................................... 119 5-18 Arbitration Cycles......................................................................................... 121 5-19 APIC Message Formats............................................................................... 121 5-20 EOI Message ............................................................................................... 122 26 ® ICH4 System Power Planes................................................................. 63 ® ICH4-M and System Clock Domains ................................................... 71 ® ICH4 Response to Sync Failures......................................................... 95 ® Intel 82801DBM ICH4-M Datasheet ...
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... NMI Sources ................................................................................................138 5-32 Frequency Strap Behavior Based on Exit State...........................................139 5-33 Frequency Strap Bit Mapping ......................................................................139 5-34 General Power States for Systems Using Intel 5-35 State Transition Rules for Intel 5-36 System Power Plane....................................................................................143 5-37 Causes of SMI# and SCI .............................................................................144 5-38 Break Events ...
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... Input Slot 1 Bit Definitions............................................................................ 250 5-102 Output Tag Slot 0......................................................................................... 252 5-103 AC-link State during PCIRST#..................................................................... 255 6-1 PCI Devices and Functions ......................................................................... 258 6-2 Fixed I/O Ranges Decoded by Intel 6-3 Variable I/O Decode Ranges ....................................................................... 262 6-4 Memory Decode Ranges from Processor Perspective ................................ 263 7-1 LAN Controller PCI Configuration Register Address Map (LAN Controller— ...
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... Test Mode Selection ....................................................................................579 19-2 XOR Test Pattern Example..........................................................................580 19-3 XOR Chain 1 ...............................................................................................581 19-4 XOR Chain 2 ...............................................................................................582 ® Intel 82801DBM ICH4-M Datasheet ® ICH4 Audio Mixer Register Configuration ..........................................501 ® ICH4 Modem Mixer Register Configuration .......................................523 ® ICH4 Ball List .....................................................................................536 ...
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... XOR Chain 4-2 ........................................................................................... 585 19-8 XOR Chain 6 ............................................................................................... 585 19-9 LONG XOR Chain ....................................................................................... 586 A-1 Intel A-2 Intel A-3 Intel 30 ® ICH4 PCI Configuration Registers ..................................................... 589 ® ICH4 Fixed I/O Registers ................................................................... 599 ® ICH4 Variable I/O Registers............................................................... 601 ® Intel 82801DBM ICH4-M Datasheet ...
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... Revision History Document Number 252337 ® Intel 82801DBM ICH4-M Datasheet Revision Description 001 Initial release Date January 2003 31 ...
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... This page is intentionally left blank. ® Intel 82801DBM ICH4-M Datasheet ...
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... Chapter 4 provides a list of each clock domain associated with the ICH4 in an ICH4-based system. ® Intel 82801DBM ICH4-M Datasheet Specification Introduction Table 1-1 for the complete Location http://developer.intel.com/design/chipsets/ industry/lpc.htm http://developer.intel.com/ial/ scalableplatforms/audio/index.htm http://www.intel.com/labs/manage/wfm/ index.htm http://www.smbus.org/specs/ http://pcisig.com/specifications.htm http://www.t13.org http://www.usb.org http://www.acpi.info http://developer.intel.com/technology/usb/ ehcispec.htm 33 ...
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... Chapter 15 provides a detailed description of all registers that reside in the modem controller. This controller resides at Device 31, Function 6 (D31:F6). Note that this chapter of the datasheet does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC- link to the codec where the registers reside. 34 ® Intel 82801DBM ICH4-M Datasheet ...
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... Chapter 18. Package Information Chapter 18 provides drawings of the physical dimensions and characteristics of the 421-BGA package. Chapter 19. Testability Chapter 19 provides detail about the implementation of test modes provided in the ICH4. Index This document ends with indexes of registers and register bits. ® Intel 82801DBM ICH4-M Datasheet Introduction 35 ...
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... The LAN controller is located on Bus 1. Function Description Hub Interface to PCI Bridge PCI to LPC Bridge IDE Controller SMBus Controller AC’97 Audio Controller AC’97 Modem Controller USB UHCI Controller #1 USB UHCI Controller #2 USB UHCI Controller #3 USB 2.0 EHCI Controller LAN Controller 2 C ® Intel 82801DBM ICH4-M Datasheet ...
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... Controllers, Timers, Power Management, System Management, GPIO, and RTC. Note that in the current chipset platform, the Super I/O (SIO) component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs. ® Intel 82801DBM ICH4-M Datasheet for details). Introduction Section 5 ...
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... The ICH4 supports 6 USB 2.0 ports. All six ports are high-speed, full-speed, and low-speed capable. ICH4’s port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. See F1 and F2) and Section 5.17, “USB EHCI Controller (D29:F7) 38 Section 5.16, “USB UHCI Controllers (D29:F0, for details. ® Intel 82801DBM ICH4-M Datasheet ...
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... The ICH4’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the ICH4 supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of ® Intel 82801DBM ICH4-M Datasheet for details devices ...
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... Alert On LAN*. The ICH4 supports Alert On LAN* and Alert On LAN response to a TCO event (intruder detect, thermal event, processor not booting) the ICH4 sends a message over the SMBus. A LAN controller can decode this SMBus message and send a message over the network to alert the network manager. 40 ® Intel 82801DBM ICH4-M Datasheet ...
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... AC ’97 Digital Link. By using an audio codec, the AC ’97 digital link allows for cost-effective, high-quality, integrated audio on Intel’s chipset-based platform. In addition ’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC ’97. The ICH4-integrated digital link allows several external codecs to be connected to the ICH4 ...
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... Introduction 42 This page is intentionally left blank. ® Intel 82801DBM ICH4-M Datasheet ...
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... When “#” is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I Input Pin O Output Pin OD Open Drain Output Pin. I/O Bi-directional Input / Output Pin. ® Intel 82801DBM ICH4-M Datasheet Signal Description 43 ...
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... Signal Description ® Figure 2-1. Intel ICH4 Interface Signals Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# REQ[4:0]# REQ5# / REQB# / GPIO1 REQA# / GPIO0 GNT[4:0]# GNT5# / GNTB# / GPIO17 GNTA# / GPIO[16] PCICLK PCIRST# PLOCK# GPIO[24]/CLKRUN# CPUSLP# IGNNE# STPCLK# A20GATE CPUPWRGD DPSLP# SERIRQ PIRQ[D:A]# PIRQ[H:E] / GPIO[5:2] ...
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... Name LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC ® Intel 82801DBM ICH4-M Datasheet Description Hub Interface Signals Hub Interface Strobe/ Hub Interface Strobe Second: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface 1.5 mode this signal is not differential and is the second of the two strobe signals ...
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... Memory Write and Invalidate All command encodings not shown are reserved. The ICH4 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. Description Description Description ® Intel 82801DBM ICH4-M Datasheet ...
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... REQ[0:4]# REQ[5]# / REQ[B]# / GPIO[1] ® Intel 82801DBM ICH4-M Datasheet Device Select: The ICH4 asserts DEVSEL# to claim a PCI transaction output, the ICH4 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH4 address or an address destined for the hub interface (main memory or AGP input, DEVSEL# indicates the response to an ICH4-initiated transaction on the PCI bus ...
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... DMA but have no ISA bus. O When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the 6th PCI bus master grant output. These signal have internal pull-up resistors. Description ® Intel 82801DBM ICH4-M Datasheet ...
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... PIORDY / (PDRSTB / PWDMARDY#) SIORDY / (SDRSTB / SWDMARDY#) ® Intel 82801DBM ICH4-M Datasheet Type Primary and Secondary IDE Device Chip Selects for 100 Range: For ATA O command register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Chip Select for 300 Range: For ATA O control register block ...
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... APIC Data: These bi-directional open drain signals are used to send and I/OD receive data over the APIC bus. As inputs the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK. Description ® Intel 82801DBM ICH4-M Datasheet ...
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... USBP4N, USBP5P, USBP5N OC[5:0]# USBRBIAS USBRBIAS# ® Intel 82801DBM ICH4-M Datasheet Type Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit data/address/command signals for ports 0 and 1. These ports can be routed to USB UHCI Controller #1 or the USB EHCI I/O Controller ...
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... It can O also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC I/F. Description ® Intel 82801DBM ICH4-M Datasheet ...
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... VGATE/VRM Power Good: VGATE/VRMPWRGD is used for Intel SpeedStep technology support. This is an output from the processor’s voltage regulator to I indicate that the voltage is stable. This signal may go inactive during an Intel SpeedStep transition. Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM during C4 and S1-M states. When the signal is high, the voltage regulator outputs the lower “ ...
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... PCICLK asserted by the ICH4 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK active low output synchronous to PCICLK asserted by the ICH4 in response to one of many hardware or O software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. Description ® Intel 82801DBM ICH4-M Datasheet ...
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... PCIsets. CPU Power Good: This signal should be connected to the processor’s PWRGOOD input. To allow for Intel signal is kept high during an Intel SpeedStep technology state transition to OD prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH4’ ...
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... RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. 2. Unless entering the XOR Chain Test Mode, the RTCRST# input must always be high when all other RTC power planes are on. Description Description Description ® Intel 82801DBM ICH4-M Datasheet ...
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... NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: - The ACLINK Shutoff bit in the AC’97 Global Control Register is set Both Function 5 and Function 6 of Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled. ® Intel 82801DBM ICH4-M Datasheet Type O AC97 Reset: This signal is a master hardware reset to external Codec(s). ...
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... Not Implemented in Mobile (Assign to Native Functionality) I Fixed as Input only. Main power well. Can be used instead as PIRQ[E:H]#. Fixed as Input only. Main power well. Can be used instead as PC/PCI I REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#. Description ® Intel 82801DBM ICH4-M Datasheet ...
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... VccRTC VccPLL VBIAS V_CPU_IO Vss ® Intel 82801DBM ICH4-M Datasheet Description 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 states. 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 states. 1.5 V supply for Hub Interface 1.5 logic. ...
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... The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the “top-block swap” mode (Intel will invert A16 for all cycles targeting FWH BIOS Rising Edge of space). The status of this strap is readable via the PWROK Top_Swap bit (bit 13, D31: F0, Offset D4h) ...
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... VccSus5 rail and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail result, V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not derive the VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform design. ® Intel 82801DBM ICH4-M Datasheet Figure 2-2 1 µF 32 ...
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... XOR Chain 3 XOR Chain 4 All “Z” Reserved. DO NOT ATTEMPT Long XOR Reserved. DO NOT ATTEMPT No Test Mode Selected XOR Chain 6 XOR Chain 4 Bandgap No Test Mode Selected 5 V Supply 1 KΩ To System Table 2-21. Section 19.1 for a ® Intel 82801DBM ICH4-M Datasheet ...
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... This chapter describes the describes the system power planes for the ICH4. In addition, the ICH4 power planes and reset pin states for various signals are presented. 3.1 Power Planes ® Table 3-1. Intel ICH4 System Power Planes Plane Main I/O (3.3 V) Main Logic (1 ...
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... Signal Intel Notes Integrated Series Termination Resistor Value approximately 33 Ω ...
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... Note that the signal levels are the same in S4 and S5. ® Intel 82801DBM ICH4-M Datasheet ® Intel ICH4-M Power Planes and Pin States Tri-state. ICH4 not driving the signal high or low. ICH4 is driving the signal to a logic ‘1’ ICH4 is driving the signal to a logic ‘0’ ...
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... High High High High-Z High-Z Defined Low Low Defined High High High High High High High High High High High High Intel S1-M S3 S4/S5 Defined Off Off Defined Off Off Off Off High-Z Off Off High-Z Off Off High Off Off ...
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... CPU I/O NMI CPU I/O SMI# CPU I/O STPCLK# CPU I/O DPSLP# CPU I/O SMBCLK, Resume I/O SMBDATA ® Intel 82801DBM ICH4-M Datasheet ® Intel ICH4-M Power Planes and Pin States During Immediately 6 6 PCIRST# / after PCIRST# C3/ RSMRST# / RSMRST# Interrupts High-Z ...
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... Low Low High Low Running Running Low Running Running Unmuxed GPIO Signals High High Defined High High Defined High High Defined Intel S1-M S3 S4/S5 Defined Defined Defined Defined Off Off Cold Reset Bit Low Low (High) Low Off Off Low Off ...
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... PIORDY PME# Resume I/O PWRBTN# Resume I/O PWROK RCIN# REQ[0:5]# REQ[B:A]# ® Intel 82801DBM ICH4-M Datasheet Intel Driver During Reset Power Supply Main I/O External Microcontroller Main I/O AC ’97 Codec AC ’97 Codec Main I/O AGP Component Main I/O Clock Generator Main I/O ...
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... Driven Static Low Low Driven High Low Low Driven Static Low Low Driven Driven Driven Driven Driven Driven Driven Driven Driven Driven Low Low Driven Driven High High Driven Driven Driven Driven Driven Driven Low Low ® Intel 82801DBM ICH4-M Datasheet ...
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... Table 4-1 shows the system clock domains. various system components, including the clock generator. For complete details of the system clocking solution refer to the system’s clock generator component specification. ® Table 4-1. Intel ICH4-M and System Clock Domains Clock Frequency Domain ...
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... Figure 4-1. Conceptual System Clock Diagram ICH4 32 kHz XTAL 72 66 MHz 33 MHz APIC CLK Clock 14.31818 MHz Gen. 48 MHz STP_CPU# STP_PCI# SLP_S1# 12.288 MHz AC’97 Codec(s) 50 MHz LAN Connect SUSCLK (32 kHz) Intel PCI Clocks (33 MHz) 14.31818 MHz 48 MHz ® 82801DBM ICH4-M Datasheet ...
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... Special Cycle with the Shutdown message type. • Device Number (AD[15:11]) = 11111 • Function Number (AD[10:8]) = 111 • Register Number (AD[7:2]) = 000000 • Data = 00h • Bus number matches secondary bus number ® Intel 82801DBM ICH4-M Datasheet Functional Description 73 ...
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... PCI devices. The conceptual logic diagrams in all sources of SERR#, along with their respective enable and status bits. ICH4 error reporting logic is configured for NMI# generation. 74 Figure 5-1 and Figure 5-2 illustrate Figure 5-3 shows how the ® Intel 82801DBM ICH4-M Datasheet ...
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... Figure 5-2. Secondary Status Register Error Reporting Logic PCI Delayed Transaction Timeout D31:F0 D31_ERR_CFG [SERR_DTT_EN] LPC Device Signaling an Error IOCHK# via SERIRQ D31:F0 D31_ERR_CFG Received Target Abort ® Intel 82801DBM ICH4-M Datasheet AND D30:F0 BRIDGE_CNT [SERR# Enable] AND D30:F0 CMD [SERR_EN] D30:F0 ERR_STS ...
Page 76
... TCO1_CNT [NMI_NOW] AND D30:F0 PD_STS [DPD] AND D30:F0 SECSTS [DPD] AND D31:F0 PCISTA [DPED] [PER] Figure 5-3 details all the parity errors that the ICH4 can detect, along To NMI# Output AND and OR Gating Logic OR NMI_EN [NMI_EN] ® Intel 82801DBM ICH4-M Datasheet ...
Page 77
... The ICH4 will always drive 0s on bits AD[15:11] when converting Type 1 configurations cycles to Type 0 configuration cycles on PCI. 3. Address bits [10:1] will also be passed unchanged to PCI. 4. Address bit 0 will be changed to 0. ® Intel 82801DBM ICH4-M Datasheet AD[31:11] During Address Phase of Type 0 Cycle on PCI 29 30 ...
Page 78
... Backward compatible software with 82557, 82558, and 82559 • TCP/UDP checksum off load capabilities • Support for Intel’s Adaptive Technology 5.2.1 LAN Controller Architectural Overview Figure 5 high level block diagram of the ICH4 integrated LAN Controller divided into four main subsystems: a Parallel subsystem, a FIFO subsystem and the Carrier-Sense Multiple Access with Collision Detect (CSMA/CD) unit ...
Page 79
... Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the LAN Controller to execute commands and receive incoming frames simultaneously, with no real-time processor intervention. ® Intel 82801DBM ICH4-M Datasheet EEPROM Interface PCI Target and ...
Page 80
... Mbps Ethernet LAN Connect components. The CSMA/CD unit performs all of the functions of the 802.3 protocol (e.g., frame formatting, frame stripping, collision handling, deferral to link traffic, etc.). The CSMA/CD unit can also be placed in a full-duplex mode, which allows simultaneous transmission and reception of frames. 80 ® Intel 82801DBM ICH4-M Datasheet ...
Page 81
... Controller controls the TRDY# signal and provides valid data on each data access. The LAN Controller allows the processor to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The processor can insert wait- states by deasserting IRDY# when it is not ready. ® Intel 82801DBM ICH4-M Datasheet Functional Description 81 ...
Page 82
... The LAN Controller, when detecting system error, will claim the cycle if it was the target of the transaction and continue the transaction as if the address was correct. Note: The LAN Controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction. 82 ® Intel 82801DBM ICH4-M Datasheet ...
Page 83
... IRDY# to support zero wait-state burst cycles. The LAN Controller also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signals completion of a data phase by deassertion and assertion of TRDY#. ® Intel 82801DBM ICH4-M Datasheet Functional Description 83 ...
Page 84
... There are at least DWords of data space left in the system memory buffer. • The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1b. • The MWI Enable bit in the LAN Controller Configure command should is set to 1b. 84 ® Intel 82801DBM ICH4-M Datasheet ...
Page 85
... LAN Controller also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the LAN Controller during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). ® Intel 82801DBM ICH4-M Datasheet Functional Description 85 ...
Page 86
... MHz) for proper operation. The LAN Controller supports a dynamic standby mode. In this mode, the LAN Controller is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the LAN Controller and is transparent to the software. 86 ® Intel 82801DBM ICH4-M Datasheet ...
Page 87
... The integrated LAN Controller uses the PCIRST# or the PWROK signal as an indication to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN Controller PCI Configuration Space, MAC configuration, and memory structure are initialized while preserving the PME# signal and its context. ® Intel 82801DBM ICH4-M Datasheet Functional Description 87 ...
Page 88
... The LAN Controller reports a PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command. 88 ® Intel 82801DBM ICH4-M Datasheet ...
Page 89
... An EEPROM read instruction waveform is shown in Figure 5-5. Figure 5-5. 64-Word EEPROM Read Instruction Waveform EE_SHCLKK EE_CS EE_DIN EE_DOUT The LAN Controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch and Dh) of the EEPROM after the deassertion of Reset. ® Intel 82801DBM ICH4-M Datasheet ...
Page 90
... IA, regardless of the U/L bit value. This configuration only affects the LAN Controller specific IA and not multicast, multi-IA, or broadcast address filtering. The LAN Controller does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit. 90 ® Intel 82801DBM ICH4-M Datasheet ...
Page 91
... Note: On the SMB, the send heartbeat packet command is not normally used in the D0 power state. The one exception in which it is used in the D0 state is when the system is hung. In normal operating mode, the heartbeat packets are transmitted through the ICH4 integrated LAN controller software similar to other packets. ® Intel 82801DBM ICH4-M Datasheet Functional Description 91 ...
Page 92
... Figure 5-6. LPC Interface Diagram ICH4 SUS_STAT# 92 Figure 5-6. Note that the ICH4 implements all of the signals that PCI Bus PCI PCI CLK RST# LAD[3:0] LFRAME# LDRQ# (optional) LPCPD# (optional) LSMI# GPI (optional) PCI PCI PME# SERIRQ Super I/O ® Intel 82801DBM ICH4-M Datasheet ...
Page 93
... Grant for bus master 0 0011 Grant for bus master 1 1111 Stop/Abort: End of a cycle for a target. NOTE: All other encodings are RESERVED. ® Intel 82801DBM ICH4-M Datasheet Table 5-2 shows the cycle types supported by the ICH4. Comment Single: 1 byte only Single: 1 byte only 1 byte only ...
Page 94
... Definition I/O Read I/O Write Memory Read Memory Write DMA Read DMA Write Reserved peripheral performing a bus master cycle generates this value, the ICH4 will abort the cycle. Table 5-5. Size Table 5-6. Indication ® Intel 82801DBM ICH4-M Datasheet ...
Page 95
... There are several error cases that can occur on the LPC interface. case and the ICH4 response. ® Table 5-7. Intel ICH4 Response to Sync Failures ICH4 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after 4 consecutive clocks. This could occur if the processor tries to access location to which no device is mapped ...
Page 96
... CYCTYPE Clock Dir & Size Clocks Clocks Clocks Start ADDR TAR Sync CYCTYPE Dir & Size Too many Syncs causes timeout Data Sync Start TAR Clocks Clocks Clock Chipset will Peripheral must drive high stop driving ® Intel 82801DBM ICH4-M Datasheet ...
Page 97
... Note: The ICH4 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are ® Intel 82801DBM ICH4-M Datasheet Functional Description 97 ...
Page 98
... DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register ® Figure 5-9. Intel ICH4 DMA Controller Each DMA channel is hardwired to the compatible settings for DMA device size: channels 3–0 are hardwired to 8-bit, count-by-bytes transfers, and channels 7– ...
Page 99
... Similarly bit address is 020000h and decrements, the next address will be 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. ® Intel 82801DBM ICH4-M Datasheet Functional Description Section 9 ...
Page 100
... DMA service, without processor intervention, as soon as a valid DREQ is detected. 100 Current Byte/Word Count Register Bytes Words Table 5-9. 16-Bit I/O Programmed Address 8-Bit I/O Programmed Address (Ch 0–3) A0 A[16:1] A[23:17] ® Intel Current Address Increment/Decrement 1 1 (Ch 5–7) (Shifted) 0 A[15:0] A[23:17] 82801DBM ICH4-M Datasheet ...
Page 101
... Clear Mask Register This command clears the mask bits of all four channels, enabling them to accept DMA requests. I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7. ® Intel 82801DBM ICH4-M Datasheet Functional Description 101 ...
Page 102
... DMA channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2]=[0,0,1,1] grants DMA channel 6 to the requesting device. 102 Start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Figure 5-10. For example, the sequence [start, bit 0, bit 1, bit 2]=[0,1,0,0] Start Bit0 Bit1 Bit2 ® Intel 82801DBM ICH4-M Datasheet ...
Page 103
... The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA "fly-by" cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory read or memory write bus cycle, its address representing the selected memory. ® Intel 82801DBM ICH4-M Datasheet Functional Description 103 ...
Page 104
... DMA cycles. BE[3:0]# 1110b 1100b I/O Read I/O Read 5-10. PCI Data Bus Connection AD[7:0] AD[15:0] Description 8-bit DMA I/O Cycle: Channels 0-3 16-bit DMA I/O Cycle: Channels 5-7 ® Intel 82801DBM ICH4-M Datasheet ...
Page 105
... This allows multiple DMA agents behind an I/O device to request use of the LPC interface and the I/O device does not need to self-arbitrate before sending the message. Figure 5-11. DMA Request Assertion Through LDRQ# LCLK LDRQ# ® Intel 82801DBM ICH4-M Datasheet Figure 5-11 Start MSB LSB ...
Page 106
... The ICH4 turns the bus around and waits for data. — The peripheral indicates data ready through SYNC and transfers the first byte. — bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. 106 ® Intel 82801DBM ICH4-M Datasheet ...
Page 107
... SYNC value of 1001b to the ICH4, the data will be transferred and the DMA request will remain active to the 8237 later time, the ICH4 will then come back with another START another transfer to the peripheral. ® Intel 82801DBM ICH4-M Datasheet CYCTYPE CHANNEL SIZE etc. combination to initiate – ...
Page 108
... To that end recommended that future devices which may appear on the LPC bus, which require higher bandwidth than 8-bit or 16-bit DMA allow with a bus mastering interface and not rely on the 8237. 108 ® Intel 82801DBM ICH4-M Datasheet ...
Page 109
... A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting will be affected as described in the mode definitions. The new count must follow the programmed count format. ® Intel 82801DBM ICH4-M Datasheet Functional Description 109 ...
Page 110
... Output goes to 1 when counter rolls over, and counter is reloaded, etc. Output is 1. Output goes to 0 when count expires for one clock time. Output is 1. Output goes to 0 when count expires for one clock time. Description ® Intel 82801DBM ICH4-M Datasheet ...
Page 111
... The next one or two reads, depending on whether the counter is programmed for one or two type counts, return the latched count. Subsequent reads return unlatched count. ® Intel 82801DBM ICH4-M Datasheet Functional Description 111 ...
Page 112
... State Machine output based on processor FERR# Internal assertion. IRQ14 from input signal (primary IDE in legacy mode Primary IDE cable only) or via SERIRQ IRQ15 from input signal (secondary IDE in legacy mode Secondary IDE Cable only) or via SERIRQ Table 5-14 Connected Pin / Function ® Intel 82801DBM ICH4-M Datasheet ...
Page 113
... Table 5-16. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 ® Intel 82801DBM ICH4-M Datasheet defines the IRR, ISR and IMR. Description Bits [7:3] ICW2[7:3] Functional Description Bits [2:0] 111 110 101 100 ...
Page 114
... Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set Special mask mode is cleared and Status Read is set to IRR. 114 ® Intel 82801DBM ICH4-M Datasheet ...
Page 115
... ICW4 The final write in the sequence, ICW4, must be programmed both controllers. At the very least, bit 0 must be set indicate that the controllers are operating in an Intel Architecture-based system. 5.7.3 Operation Command Words (OCW) These command words reprogram the Interrupt Controller to operate in various interrupt modes. • ...
Page 116
... ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read will contain bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. 116 ® Intel 82801DBM ICH4-M Datasheet ...
Page 117
... From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. ® Intel 82801DBM ICH4-M Datasheet Functional Description 117 ...
Page 118
... However, active low non-ISA interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH4 receives the PIRQ input, like all of the other external sources, and routes it accordingly. 118 ® Intel 82801DBM ICH4-M Datasheet ...
Page 119
... IRQ # SERIRQ Yes Yes 4 Yes 5 Yes 6 Yes 7 Yes Yes 10 Yes 11 Yes 12 Yes ® Intel 82801DBM ICH4-M Datasheet Direct from Via PCI pin message No No Cascade from 8259 #1 No Yes No No 8254 Counter 0 No Yes No Yes No Yes No Yes No Yes No No RTC No Yes ...
Page 120
... USB UHCI Controller #3, Native IDE PIRQ[D]# No USB UHCI Controller #2 PIRQ[E]# Yes LAN, option for SCI, TCO PIRQ[F]# Yes Option for SCI, TCO PIRQ[G]# Yes Option for SCI, TCO PIRQ[H]# Yes USB EHCI Controller, option for SCI, TCO Internal Modules ® Intel 82801DBM ICH4-M Datasheet ...
Page 121
... Delivery Mode bits. Table 5-19. APIC Message Formats Message Cycles EOI Short Lowest Priority Remote Read ® Intel 82801DBM ICH4-M Datasheet describes the arbitration cycles. Bit 0 0 Bit Normal, Bit EOI 1 1 Arbitration ID. If ICH4 samples a different value than it sent, it lost arbitration. ...
Page 122
... NOT(A) 13 NOT(A1) 14 122 Bit 1 Bit EOI message ARBID 1 Arbitration ID Interrupt vector bits from redirection table NOT(V6) register NOT(V4) NOT(V2) NOT(V0) NOT(C0) Check Sum from Cycles 6– Postamble NOT(A) Status Cycle 0 NOT(A1) Status Cycle Idle Comments ® Intel 82801DBM ICH4-M Datasheet ...
Page 123
... Cycle 19 and 20 indicates the status of the message (i.e., accepted, check sum error, retry, or error). status signal combinations and their meanings for all delivery modes. ® Intel 82801DBM ICH4-M Datasheet Bit 0 Comments ...
Page 124
... Error 01 Error 00 Checksum Error Checksum OK: No Focus 11 Processor 10 Error Checksum OK: Focus 01 Processor 00 Checksum Error 11 Checksum OK 10 Error 01 Error 00 Checksum Error A1 Comments 1x Error 01 Accepted 00 Retry Error 01 Accepted 00 Error Error 01 End and Retry 00 Go for Low Priority Arbitration ® Intel 82801DBM ICH4-M Datasheet ...
Page 125
... Only the local APICs that have "free interrupt slots" will participate in the lowest priority arbitration. 2. Cycles 29 through 32 are used to break a tie in case two more processors have lowest priority. The bus arbitration IDs are used to break the tie. ® Intel 82801DBM ICH4-M Datasheet Bit 0 Comments 0 ...
Page 126
... Status Cycle 0. NOT(A1) Status Cycle 1. d30 d28 d26 d24 d22 d20 d18 d16 Remote register data 31-0 d14 d12 d10 d08 d06 d04 d02 d00 S Data Status valid invalid C Check Sum for data d31-d00 1 Idle Comments ® Intel 82801DBM ICH4-M Datasheet ...
Page 127
... PCI PIRQ[A:D], those received via SERIRQ#, or the internal level-triggered interrupts such as SCI or TCO). The ICH4 ignores interrupt messages sent by PCI masters that attempt to use IRQ0 13. ® Intel 82801DBM ICH4-M Datasheet Functional Description 127 ...
Page 128
... In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the interrupt is still active. 128 Section 5.8.5.5. ® Intel 82801DBM ICH4-M Datasheet ...
Page 129
... Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used, 2 and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00. ® Intel 82801DBM ICH4-M Datasheet Table 5-25 and Table 5-26 for the Address and Data. Description ...
Page 130
... IRQ protocol does not support the additional APIC interrupts (20–23). Note: When the IDE primary and secondary controllers are configured for native IDE mode, the only way to use the internal IRQ14 and IRQ15 connections to the Interrupt Controllers is through the Serial Interrupt pin. 130 Description ® Intel 82801DBM ICH4-M Datasheet ...
Page 131
... The number of clocks determines the next mode: Table 5-27. Stop Frame Explanation Stop Frame Width 2 PCI clocks 3 PCI clocks ® Intel 82801DBM ICH4-M Datasheet Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame Continuous Mode. Only the host (ICH4) may initiate a Start Frame Functional Description ...
Page 132
... Ignored. IRQ8# can only be generated internally or on ISA Ignored. IRQ13 can only be generated from FERR not include in BM IDE interrupt logic 47 Do not include in BM IDE interrupt logic 50 Same as ISA IOCHCK# going active. 53 Drive PIRQA# 56 Drive PIRQB# 59 Drive PIRQC# 62 Drive PIRQD# Intel Comment ® 82801DBM ICH4-M Datasheet ...
Page 133
... To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. ® Intel 82801DBM ICH4-M Datasheet Functional Description Section 5.10.4 ...
Page 134
... BIOS can monitor the state of this bit and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST pulled up through a weak pull-up resistor. state when RTCRST# is asserted. 134 Table 5-29 shows which bits are set to their default ® Intel 82801DBM ICH4-M Datasheet ...
Page 135
... Then, once booted, the RTC_PWR_STS can be detected in the set state. Note: Clearing CMOS, using a jumper on VCCRTC, must not be implemented. ® Intel 82801DBM ICH4-M Datasheet Default State Register ...
Page 136
... Standard Input from processor: FERR# • Intel SpeedStep technology Output to processor: CPUPWRGOOD Most ICH4 outputs to the processor use standard buffers. The ICH4 has a separate VCC signal which is pulled up at the system level to the processor voltage, and thus determines V outputs to the processor. Note that this is different than previous generations of chips, that have used open-drain outputs ...
Page 137
... I/O Write to F0h IGNNE# If COPROC_ERR_EN is not set, then the assertion of FERR# will have not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. ® Intel 82801DBM ICH4-M Datasheet Functional Description Comment transition on RCIN# must occur before the ICH4 will arm INIT generated again. ...
Page 138
... CPUPWRGOOD Signal This signal is connected to the processor’s PWRGOOD input. To allow for Intel SpeedStep technology support, this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH4’s PWROK and VGATE / VRMPWRGD signals ...
Page 139
... NOTE: The FREQ_STRAP register is in the RTC well. The value in the register can be forced to 1111h via a pinstrap (AC_SDOUT signal), or the ICH4 can automatically force the speed strapping to 1111h if the processor fails to boot. Figure 5-13. Signal Strapping Processor A20M#, IGNNE#, INTR, NMI ® Intel 82801DBM ICH4-M Datasheet ICH4 Sets High/Low Level for the Corresponding Signal ...
Page 140
... ACPI S3 state: Suspend to RAM (STR) — ACPI S4 state: Suspend-to-Disk (STD) — ACPI G2/S5 state: Soft Off (SOFF) — Power Failure Detection and Recovery • Streamlined Legacy Power Management Support for APM-Based Systems • Intel SpeedStep technology transition logic 140 ® Intel 82801DBM ICH4-M Datasheet ...
Page 141
... Grant cycle, halts its instruction stream. ICH4 then asserts STP_CPU#, which forces the clock G0/S0/C3 generator to stop the processor clock. This is also used for Intel SpeedStep technology support. Accesses to memory (by AGP, PCI, or internal units) is not permitted while state assumed that the ARB_DIS bit is set prior to entering C3 state. ...
Page 142
... For example, in going from S0 to S1-M, it may appear to pass through the G0/S0/C2 states. These intermediate transitions and states are not listed in the table. Table 5-35. State Transition Rules for Intel Present State • ...
Page 143
... PIRQ or not; (see Section 9.1.11 ACPI Control Register for SCI sources are removed. ® Intel 82801DBM ICH4-M Datasheet By SLP_S1# puts the clock generator into a low-power state, but does not cut the power to the processor. The SLP_S3# signal can be used to cut the processor’ ...
Page 144
... TCO SMI -Write attempted to BIOS BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event Classic USB Legacy logic Serial IRQ SMI reported 144 SCI SMI Additional Enables Yes ...
Page 145
... Level 2 register in the ICH4. The C3 state is entered based on the processor reading the Level 3 register in the ICH4. Note that an Intel SpeedStep technology transition may appear to temporarily pass through a C3 state, however separate transition and documented separately in The C4 state is entered based on the processor reading the Level 4 register in the ICH4 reading the Level 3 register when the C4onC3_EN bit is set ...
Page 146
... Many possible sources Could be indicated by the keyboard controller C2, C3, C4 via the RCIN input signal. C3, C4 Need to wake up processor so it can do snoops. Only available if FERR# enabled for break event C2, C3, C4 indication (See GEN_CNTL.FERR# Mux-En bit in Section Comment 9.1.22). ® Intel 82801DBM ICH4-M Datasheet ...
Page 147
... If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop- Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should return to the C1 state. ® Intel 82801DBM ICH4-M Datasheet Functional Description 147 ...
Page 148
... After observing the CLKRUN# signal asserted for 1 clock, the ICH4 again starts asserting the signal. • internal device needs the PCI bus, the ICH4 asserts the CLKRUN# signal. 148 ® Intel 82801DBM ICH4-M Datasheet ...
Page 149
... Delayed Transaction on PCI. CLKRUN# should stay low until the cycle completes (without Delayed Transaction). • Any bus master below PCI that needs to run a cycle. This could include the Processor System Bus interrupt logic for the I/O APIC downstream of PCI. ® Intel 82801DBM ICH4-M Datasheet Functional Description 149 ...
Page 150
... SLP_EN bit disables thermal throttling (since S1-M–S5 sleep state has higher priority). • The G3 state cannot be entered via any software mechanism. The G3 state indicates a complete loss of power. 150 ® Intel 82801DBM ICH4-M Datasheet ...
Page 151
... This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted will be latched by the ICH4, and the system will wake after BATLOW# is deasserted. ® Intel 82801DBM ICH4-M Datasheet for details on going to the state. Comment software does not mask all interrupts in I/O APIC prior to entering S1-M, the system may hang during resume from S1-M ...
Page 152
... Hard Reset System (See Command Table 5-41 summarizes the use of GPIs as wake events. Power Well Wake From Core S1-M Resume S1-M–S5 How Enabled – – being able to wake from S1-M S5. Notes ACPI Compliant ® Intel 82801DBM ICH4-M Datasheet ...
Page 153
... Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST# and PME_STS is cleared by RSMRST#. Table 5-42. Transitions Due to Power Failure State at Power Failure S0, S1- ® Intel 82801DBM ICH4-M Datasheet AFTERG3_EN bit Transition When Power Returns ...
Page 154
... If this bit is set, the ICH4 starts throttling using the ratio in the THRM_DTY field. When this bit is cleared, the ICH4 stops throttling, unless the THRM# signal has been active for 2 seconds or if the THTL_EN bit is set (indicating that ACPI software is attempting throttling). 154 ® Intel 82801DBM ICH4-M Datasheet ...
Page 155
... SpeedStep performance/thermal states and to transition smoothly between them. The internal processor clock setting and processor supply voltage setting determine these states. The ICH4 supports a low- power mode and a high-performance mode. ® Figure 5-14. Intel SpeedStep Enabled Mobile ® Intel 82801DBM ICH4-M Datasheet ® ...
Page 156
... MSR or in the CPUID register. The ICH4 is not capable of determining whether it is attached to a processor with or without Intel SpeedStep technology. When used a processor without Intel SpeedStep technology, software should not write or read the ICH4 Intel SpeedStep technology registers. ...
Page 157
... Once the system has resumed to the S0 state, the 4-second timer starts. ® Intel 82801DBM ICH4-M Datasheet Table 5-43. Note that the transitions start as soon as the PWRBTN# is ...
Page 158
... Once a reset of this type has occurred, it cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state as indicated by all of the PWROK inputs being active. 158 Event RI_EN RI# Active X 0 RI# Active 1 Table 5-44 shows Event Ignored Ignored Wake Event ® Intel 82801DBM ICH4-M Datasheet ...
Page 159
... ICH4 implements an ALT access mode. If the ALT access mode is entered and exited after reading the registers of the ICH4 timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below can cause problems: ® Intel 82801DBM ICH4-M Datasheet Functional Description 159 ...
Page 160
... Timer Counter 2 base count 7 high byte Timer Counter 1 status, bits [5:0] Timer Counter 2 status, bits [5:0] Bit 7 = NMI Enable, Bits [6:0] = RTC Address DMA Chan 5 base address low 1 byte DMA Chan 5 base address high 2 byte ® Intel 82801DBM ICH4-M Datasheet ...
Page 161
... PIC ICW4 of Slave controller PIC OCW1 of Slave 10 controller 11 PIC OCW2 of Slave controller 12 PIC OCW3 of Slave controller NOTES: 1. The OCW1 register must be read before entering ALT access mode. 2. Bits and 0 return 0. ® Intel 82801DBM ICH4-M Datasheet I Data Access Addr Rds C6h 2 C8h 2 ...
Page 162
... PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-46. Table 5-46. PIC Reserved Bits Return Values PIC Reserved Bits ICW2[2:0] ICW4[7:5] ICW4[3:2] ICW4[0] OCW2[4:3] OCW3[7] OCW3[5] OCW3[4:3] 162 Value Returned 000 000 Reflects bit 6 01 ® Intel 82801DBM ICH4-M Datasheet ...
Page 163
... RTC clock period may not be detected by the ICH4 the case of true PWROK failure, PWROK will go low first before the VRMPWRGD/ VGATE. ® Intel 82801DBM ICH4-M Datasheet Table 5-47 have write paths to them in ALT access mode. Software Register Write Value DMA Status Register for channels 0– ...
Page 164
... VGATE Signal VGATE is an input from the regulator indicating that all of the outputs from the regulator are on and within specification. When the system is performing an Intel SpeedStep transition between performance states, the voltage regulator output may be required to change not desirable, however, that CPUPWRGD becomes deasserted during these transitions. Normally, this would indicate to the system that a power-on reset be performed, which would invalidate the system context ...
Page 165
... Clock Generators The clock generator is expected to provide the frequencies shown in Table 5-48. Intel ICH4 Clock Inputs Clock Frequency Domain CLK66 66 MHz PCICLK 33 MHz CLK48 48 MHz CLK14 14.318 MHz AC_BIT_CLK 12.288 MHz 16.67 MHz APICCLK or 33 MHz 0.8 to LAN_CLK 50 MHz 5.12.13.1 ...
Page 166
... When software (not the SMI# handler) attempts to access the device, a trap occurs (the cycle does not really go to the device and an SMI# is generated). 3. The SMI# handler turns on the device and turns off the trap The SMI# handler exits with an I/O restart. This allows the original software to continue. 166 ® Intel 82801DBM ICH4-M Datasheet ...
Page 167
... The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. ® Intel 82801DBM ICH4-M Datasheet Section 8.1.26) Functional Description ...
Page 168
... The event messages are sent based on events occurring. The heartbeat messages is sent every seconds. When an event occurs, the ICH4 sends a new message and increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment. 168 Section 5.13.2). Intel ® 82801DBM ICH4-M Datasheet ...
Page 169
... If the intervention occurs before the third timeout, then jump to rule/step11. 4. After step 3 (third timeout), if the user does a Power Button Override, the system goes state. The ICH4 continues sending heartbeats at this point. ® Intel 82801DBM ICH4-M Datasheet Functional Description 169 ...
Page 170
... SMBus rules associated with collision detection. It delays starting a message until the bus is idle, and will detect collisions collision is detected, the ICH4 waits until the bus is idle and tries again. 170 timeout reset is attempted (using a button that pulses PWROK low or via ® Intel 82801DBM ICH4-M Datasheet ...
Page 171
... TCO Timer Event Status Software Event Status Unprogrammed FWH Event Status GPIO Status ® Intel 82801DBM ICH4-M Datasheet Comment 1 = This bit will be set if the intruder detect bit is set (INTRD_DET This bit will be set if the ICH4 THERM# input signal is asserted This bit will be set if the processor failed to fetch the first instruction. ...
Page 172
... MSB (SEQ3) sent first Pre-Boot. MSB sent first Will be the same as the MESSAGE1 Register. MSB sent first. Will be the same as the MESSAGE2 Register. MSB sent first. Will be the same as the WDSTATUS Register. MSB sent first. ® Intel 82801DBM ICH4-M Datasheet ...
Page 173
... Input GPI[8] Only GPIO[10:9] N/A Input GPI[11] Only Input GPI[12] Only Input GPI[13] Only GPIO[15:14] N/A Output GPO[16] Only ® Intel 82801DBM ICH4-M Datasheet Alternate Power Tolerant (1) Function Well REQ[A]# Core 5.0 V REQ[B]# or Core 5.0 V REQ[5]# PIRQ[E:H]# Core 5.0 V N/A N/A ...
Page 174
... Output controlled via GP_LVL register bit 25. • TTL driver output • Not implemented • Input active status read from GP_LVL register bits [27:28] • Output controlled via GP_LVL register bits [27:28] • TTL driver output • Not implemented ® Intel 82801DBM ICH4-M Datasheet ...
Page 175
... Command and Control Block registers are accessible at fixed I/O addresses. While in legacy mode, the ICH4 does not decode any of the native mode ranges. Likewise, in native mode the ICH4 does not decode any of the legacy mode ranges. ® Intel 82801DBM ICH4-M Datasheet Functional Description 175 ...
Page 176
... Sector Number Cylinder Low Cylinder High Head Command Register Function (Read) Reserved Reserved Device Control Forward to LPC - Not Claimed by IDE above. However, the base addresses are selected using the PCI BARs, Register Function (Write) Register Function (Write) ® Intel 82801DBM ICH4-M Datasheet ...
Page 177
... For compatible timings, a shutdown and startup latency is incurred between the two 16-bit halves of the IDE transaction. This guarantees that the chip selects will be deasserted for at least two PCI clocks between the two cycles. ® Intel 82801DBM ICH4-M Datasheet Table 5-53. Note that bit 2 (16-bit I/O ...
Page 178
... If greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal transfer completion. 178 ® Intel 82801DBM ICH4-M Datasheet ...
Page 179
... This connection is done from the ISA pin, before any mask registers. This implies the following: • Bus Master IDE devices are connected directly off of ICH4. IDE interrupts cannot be communicated through PCI devices or the serial stream. ® Intel 82801DBM ICH4-M Datasheet Byte 2 Byte 1 Byte 0 ...
Page 180
... Software issues the appropriate DMA transfer command to the disk device. 4. The bus master function is engaged by software writing the Start bit in the Command Register. The first entry in the PRD table is fetched and loaded into two registers which are not 180 ® Intel 82801DBM ICH4-M Datasheet ...
Page 181
... A System hang may occur if there exists a pending IDE interrupt status bit during Native IDE read/ write operations resulting in an apparent hang condition (Interrupt Storm). ® Intel 82801DBM ICH4-M Datasheet describes how to interpret the Interrupt and Active bits in the Status Register Functional Description ...
Page 182
... This bit combination signals an error condition. If the Error bit in the status register is set, then the controller has some problem transferring data to/from memory. Specifics of the error have to be determined using bus-specific information. If the Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size. ® Intel 82801DBM ICH4-M Datasheet ...
Page 183
... IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, the ICH4 tri-states the DD lines, deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word and STROBE. ® Intel 82801DBM ICH4-M Datasheet Ultra ATA/33 Read Ultra ATA/33 Write ...
Page 184
... The ICH4 Ultra ATA/100 logic can achieve read transfer rates up to 100-MB/s, and write transfer rates up to 88.9 MB/s. The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100 further cable improvements are required when implementing Ultra ATA/100. 184 ® Intel 82801DBM ICH4-M Datasheet ...
Page 185
... IDE drive powers down, and ensures that zeros will always be returned for read cycles that occur during hot swap operation. Warning: The software should not attempt to control the outputs (either tri-state or driving low), while an IDE transfer is in progress. Unpredictable results could occur, including a system lockup. ® Intel 82801DBM ICH4-M Datasheet Functional Description 185 ...
Page 186
... TD (Transfer Descriptor (Queue Head). This allows the ICH4 to perform the proper type of processing on the item after it is fetched Terminate (T). This bit indicates to the ICH4 whether the schedule for this frame has valid entries in it Empty Frame (pointer is invalid Pointer is valid (points TD). 186 Table 5-56. Description ® Intel 82801DBM ICH4-M Datasheet ...
Page 187
... When encountered in a queue context, this bit indicates to the ICH4 that there are no more valid entries in the queue encountered outside of a queue context with the T bit set 0 informs the ICH4 that this is the last TD in the frame Link Pointer field is valid Link Pointer field not valid. ® Intel 82801DBM ICH4-M Datasheet ...
Page 188
... The Active bit is also set stall handshake is received from the endpoint Set software to enable the execution of a message transaction by the ICH4. 188 Description 1 1 Section Intel 5.16.2, Data Transfers to/from Main ® 82801DBM ICH4-M Datasheet ...
Page 189
... Actual Length (ACTLEN). The Actual Length field is written by the ICH4 at the conclusion of a USB transaction to indicate the actual number of bytes that were transferred. It can be used by the 10:0 software to maintain data integrity. The value programmed in this register is encoded as n-1 (see Maximum Length field description in the TD Token). ® Intel 82801DBM ICH4-M Datasheet Functional Description Description 189 ...
Page 190
... This buffer must be at 31:0 least as long as the value in the Maximum Length field described int the TD token. The data buffer may be byte-aligned. 190 Description Description ® Intel 82801DBM ICH4-M Datasheet ...
Page 191
... Terminate (T). This bit indicates to the ICH4 that there are no valid TDs in this queue. When HCD has new queue entries it overwrites this value with a new TD pointer to the queue entry Pointer is valid Terminate (No valid queue entries). ® Intel 82801DBM ICH4-M Datasheet Functional Description Table 5-61. Description ...
Page 192
... The TD/QH process continues until the millisecond allotted to the current frame expires. At this point, the ICH4 fetches the next entry from the Frame List. If the ICH4 is not able to process all of the transfer descriptors during a given frame, those descriptors are retired by software without having been executed. 192 ® Intel 82801DBM ICH4-M Datasheet ...
Page 193
... If not successful, and the error count has not been reached, leave the TD active. If the error count has been reached, mark the TD inactive 12. 11. Write the link pointer from the current TD into the element pointer field of the QH structure. If the Vf bit is set in the TD link pointer 12. Proceed to next entry. ® Intel 82801DBM ICH4-M Datasheet Functional Description 193 ...
Page 194
... Set USB Error Int bit Set USB Int bit TD Status Register Actions 1 1 Clear Active bit and set Stall bit 1 Clear Active bit and set Stall bit 1 1 Clear Active bit and set Stall bit Clear Active bit ® Intel 82801DBM ICH4-M Datasheet ...
Page 195
... Frame List Pointer Link Pointer (Horiz Link Pointer (Vert) Indicates 'NULL' Queue Head Link Pointer (Horz )=Queue Head Link Pointer field in QH DWord 0 z Link Pointer (Vert)=Queue Element Link Pointer field in QH DWord 1 ® Intel 82801DBM ICH4-M Datasheet Link Pointer (Horiz ...
Page 196
... Table 5-65 lists the general queue advance criteria, which are based on Host-to-Function (OUT) Error/NAK Non-NULL Retry Q Element Advance Q Intel Table 5-65, NULL Error/NAK Advance Q Retry Q Element ® 82801DBM ICH4-M Datasheet ...
Page 197
... TD. Link Pointer QH bit bit in QH Table 5-66. USB Schedule List Traversal Decision Table Q QH.Q QH.T Context 0 — — 0 — — 0 — — ® Intel 82801DBM ICH4-M Datasheet TD QHLP TDLP QELP QE.Q QE.T TD.Vf TD.Q TD.T — — — — — — ...
Page 198
... Field formats for the token, data, and handshake packets are described in the following section. The effects of NRZI coding and bit stuffing have been removed for the sake of clarity. All packets have distinct start and end of packet delimiters. 198 Figure 5-18. ® Intel 82801DBM ICH4-M Datasheet ...
Page 199
... Special PIDs are divided into four coding groups: token, data, handshake, and special, with the first two transmitted PID bits (PID[1:0]) indicating which group. This accounts for the distribution of PID codes. ® Intel 82801DBM ICH4-M Datasheet Data Sent PID 0 PID 1 PID 2 ...
Page 200
... LSB first. 200 Data Sent Bit ADDR 0 4 ADDR 1 5 ADDR 2 6 ADDR 3 Table 5-70, permits more flexible Data Sent ENDP 0 ENDP 1 ENDP 2 ENDP 3 Intel Data Sent ADDR 4 ADDR 5 ADDR 6 Table 5-69, a ® 82801DBM ICH4-M Datasheet ...