ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 25

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1760_4
Product data sheet
The SUSPEND/WAKEUP_N pin is a 3-state output. It is also an input to the internal
wake-up logic.
When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of
the SUSPEND/WAKEUP_N pin:
The resume state has a clock-off count timer defined by bits 31 to 16 of the Power Down
Control register. The default value of this timer is 10 ms, meaning that the resume state
will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD
register is set to logic 1, the host controller will go into a permanent resume; the normal
functional state. If the RUN/STOP bit is not set during the time determined by the clock-off
count, the ISP1760 will switch back to suspend mode after the specified time. The
maximum delay that can be programmed in the clock-off count field is approximately
500 ms.
Additionally, the Power Down Control register allows the ISP1760 internal blocks to be
disabled for lower power consumption as defined in
The lowest suspend current, I
room temperature. The suspend current will increase with the increase in temperature,
with approximately 300 A at 40 C and up to a typical 1 mA at 85 C. The system is not in
suspend mode when its temperature increases above 40 C. Therefore, even a 1 mA
current consumption by the ISP1760 in suspend mode can be considered negligible. In
normal environmental conditions, when the system is in suspend mode, the maximum
ISP1760 temperature will be approximately 40 C determined by the ambient temperature
so the ISP1760 maximum suspend current will be below 300 A. An alternative solution to
achieve a very low suspend current is to completely switch off the V
using an external PMOS transistor, controlled by one of the GPIO pins of the processor.
This is possible because the ISP1760 can be used in hybrid mode, which allows only the
V
When the ISP1760 power is always on, the time from wake-up to suspend will be
approximately 100 ms.
It is necessary to wait for the CLKREADY interrupt assertion before programming the
ISP1760 because internal clocks are stopped during deep-sleep suspend and restarted
after the first wake-up event. The occurrence of the CLKREADY interrupt means that
internal clocks are running and the normal functionality is achieved.
It is estimated that the CLKREADY interrupt will be generated less than 100 s after the
wake-up event, if the power to the ISP1760 was on during suspend.
If the ISP1760 is used in hybrid mode and V
pulse is required when the power is switched back on, before the resume programming
sequence starts. This will ensure that internal clocks are running and all logics reach a
stable initial state.
•
•
CC(I/O)
If it remains pulled-up, no wake-up is generated because a HIGH is sensed by the
internal wake-up circuit.
If the pin is externally pulled LOW, for example, by the GPIO line or just as a test by
jumper, the input to the wake-up circuitry becomes LOW and the wake-up is internally
initiated.
powered on to avoid loading of the system bus.
Rev. 04 — 4 February 2008
CC(susp)
, that can be achieved is approximately 150 A at
CC(5V0)
Embedded Hi-Speed USB host controller
is off during suspend, a 2 ms reset
Table
51.
CC(5V0)
© NXP B.V. 2008. All rights reserved.
ISP1760
power input by
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