ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 45
ISP1760ET,557
Manufacturer Part Number
ISP1760ET,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1760ET557.pdf
(111 pages)
Specifications of ISP1760ET,557
Package Type
TFBGA
Pin Count
128
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
Table 42.
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Buffer Status register (address 0334h) bit allocation
8.3.6 Buffer Status register
R/W
R/W
R/W
31
23
15
0
0
0
Table 41.
The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is,
ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets
the Buffer Filled bit of a particular transfer in the Buffer Status register, the HC will start
traversing through PTD headers that are not marked for skipping and are valid PTDs.
Remark: Software can set these bits during the initialization.
Table 42
Bit
31 to 8
7 to 4
3 to 2
1
0
R/W
R/W
R/W
30
22
14
0
0
0
shows the bit allocation of the Buffer Status register.
Symbol
DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or
-
BURST_LEN[1:0]
ENABLE_DMA
DMA_READ_WRITE_
SEL
DMA Configuration register (address 0330h) bit description
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 04 — 4 February 2008
R/W
R/W
R/W
28
20
12
Description
write).
Remark: Different number of bursts will be generated for the
same transfer length programmed in 16-bit and 32-bit modes
because DMA_COUNTER is in number of bytes.
reserved
DMA Burst Length:
00 — Single DMA burst
01 — 4-cycle DMA burst
10 — 8-cycle DMA burst
11 — 16-cycle DMA burst
Enable DMA:
0 — Terminate DMA
1 — Enable DMA
DMA Read/Write Select: Indicates if the DMA operation is a
write or read to or from the ISP1760.
0 — DMA write to the ISP1760 internal RAM is set
1 — DMA read from the ISP1760 internal RAM
0
0
0
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
27
19
11
0
0
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
26
18
10
0
0
0
R/W
R/W
R/W
25
17
0
0
9
0
© NXP B.V. 2008. All rights reserved.
ISP1760
R/W
R/W
R/W
44 of 110
24
16
0
0
8
0
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