ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 15
Manufacturer Part Number
Specifications of ISP1760ET,557
Lead Free Status / RoHS Status
Product data sheet
7.1.1 Internal clock scheme and port selection
The ISP1760 has three ports.
enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by
external pull-up resistors, if not used. The DP and DM of the unused ports need not be
externally pulled HIGH because there are internal pull-down resistors on each port that
are enabled by default.
lists the various port connection scenarios.
shows that the host clock is derived from port 2. Port 2 does not need to be
ISP1760 clock scheme
Rev. 04 — 4 February 2008
PLL 12 MHz IN
AND POLLING USING
INTERNAL HUB (TT)
shows the internal clock scheme of the ISP1760.
Embedded Hi-Speed USB host controller
© NXP B.V. 2008. All rights reserved.
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