ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 15

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1760_4
Product data sheet
7.1.1 Internal clock scheme and port selection
The ISP1760 has three ports.
Figure 5
enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by
external pull-up resistors, if not used. The DP and DM of the unused ports need not be
externally pulled HIGH because there are internal pull-down resistors on each port that
are enabled by default.
Table 3
Fig 4.
Fig 5.
lists the various port connection scenarios.
shows that the host clock is derived from port 2. Port 2 does not need to be
Internal hub
ISP1760 clock scheme
Rev. 04 — 4 February 2008
XOSC
PORT1
PLL 12 MHz IN
Figure 5
AND POLLING USING
INTERNAL HUB (TT)
ENUMERATION
ACTUAL PTDs
ROOT HUB
PORTSC1
PORT2
EHCI
PORT 2
PORT 3
shows the internal clock scheme of the ISP1760.
PORT 1
ATX
ATX
ATX
Embedded Hi-Speed USB host controller
host clock:
48 MHz,
30 MHz,
60 MHz
PORT3
DIGITAL CORE
EXTERNAL
PORTS
CORE
HOST
004aaa513
004aaa535
© NXP B.V. 2008. All rights reserved.
ISP1760
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