ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Fig 4.
7.1.1 Internal clock scheme and port selection
The ISP1760 has three ports.
Fig 5.
Figure 5
enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by
external pull-up resistors, if not used. The DP and DM of the unused ports need not be
externally pulled HIGH because there are internal pull-down resistors on each port that
are enabled by default.
Table 3
ISP1760_4
Product data sheet
EHCI
ROOT HUB
PORTSC1
ENUMERATION
AND POLLING USING
ACTUAL PTDs
INTERNAL HUB (TT)
PORT2
PORT1
Internal hub
Figure 5
XOSC
PLL 12 MHz IN
ISP1760 clock scheme
shows that the host clock is derived from port 2. Port 2 does not need to be
lists the various port connection scenarios.
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
PORT3
EXTERNAL
PORTS
004aaa513
shows the internal clock scheme of the ISP1760.
host clock:
DIGITAL CORE
48 MHz,
30 MHz,
60 MHz
PORT 2
ATX
HOST
CORE
PORT 1
ATX
PORT 3
ATX
004aaa535
ISP1760
© NXP B.V. 2008. All rights reserved.
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