ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 21
Manufacturer Part Number
Specifications of ISP1760ET,557
Lead Free Status / RoHS Status
The DMA start address must be initialized in the respective register, and the subsequent
transfers will automatically increment the internal ISP1760 memory address. A register or
memory access or access to other system memory can occur in between DMA bursts,
whenever the bus is released because DACK is de-asserted, without affecting the DMA
transfer counter or the current address.
Any memory area can be accessed by the system’s DMA at any starting address because
there are no predeﬁned memory blocks. The DMA transfer must start on a word or double
word address, depending on whether the data bus width is set to 16 bit or 32 bit. DMA is
the most efﬁcient method to initialize the payload area, to reduce the CPU usage and
overall system loading.
The ISP1760 does not implement EOT to signal the end of a DMA transfer. If
programmed, an interrupt may be generated by the ISP1760 at the end of the DMA
The slave DMA of the ISP1760 will issue a DREQ to the DMA controller of the system to
indicate that it is programmed for transfer and data is ready. The system DMA controller
may also start a transfer without the need of the DREQ, if the ISP1760 memory is
available for the data transfer and the ISP1760 DMA programming is completed.
It is also possible that the system’s DMA will perform a memory-to-memory type of
transfer between the system memory and the ISP1760 memory. The ISP1760 will be
accessed in PIO mode. Consequently, memory read operations must be preceded by
initializing the Memory register (address 033Ch), as described in
will be generated by the ISP1760 on completing the DMA transfer but an internal
processor interrupt may be generated to signal that the DMA transfer is completed. This is
mainly useful in implementing the double-buffering scheme for data transfer to optimize
the USB bandwidth.
The ISP1760 DMA programming involves:
Set the active levels of signals DREQ and DACK in the HW Mode Control register.
The DMA Start Address register contains the ﬁrst memory address at which the data
transfer will start. It must be word-aligned in 16-bit data bus mode and double word
aligned in 32-bit data bus mode.
The programming of the DMA Conﬁguration register speciﬁes:
– The type of transfer that will be performed: read or write.
– The burst size, expressed in bytes, is speciﬁed, regardless of the data bus width.
For the same burst size, a double number of cycles will be generated in 16-bit
mode data bus width as compared to 32-bit mode.
– The transfer length, expressed in number of bytes, deﬁnes the number of bursts.
The DREQ will be de-asserted and asserted to generate the next burst, as long as
there are bytes to be transferred. At the end of a transfer, the DREQ will be
de-asserted and an IRQ can be generated if DMAEOTINT (bit 3 in the Interrupt
register) is set. The maximum DMA transfer size is equal to the maximum memory
size. The transfer size can be an odd or even number of bytes, as required. If the
transfer size is an odd number of bytes, the number of bytes transferred by the
system’s DMA is equal to the next multiple of two for the 16-bit data bus width or
four for the 32-bit data bus width. For a write operation, however, only the speciﬁed
odd number of bytes in the ISP1760 memory will be affected.
Product data sheet
Embedded Hi-Speed USB host controller
Rev. 04 — 4 February 2008
7.3.1. No IRQ
© NXP B.V. 2008. All rights reserved.
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