ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 22

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1760_4
Product data sheet
7.4 Interrupts
After programming the preceding parameters, the system’s DMA may be enabled, waiting
for the DREQ to start the transfer or immediate transfer may be started.
The programming of the system’s DMA must match the programming of the ISP1760
DMA parameters. Only one DMA transfer may take place at a time. PIO mode data
transfer may occur simultaneously with a DMA data transfer, in the same or a different
memory area.
The ISP1760 will assert an IRQ according to the source or event in the Interrupt register.
The main steps to enable the IRQ assertion are:
Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as
necessary, applicable only when IRQ is set to be edge-active; a pulse of a defined width is
generated every time IRQ is active.
Bits 15 to 0 of the Edge Interrupt Count register define the IRQ pulse width. The maximum
pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This
setting is necessary for certain processors that may require a different minimum IRQ
pulse width from the default value. The default IRQ pulse width set at power-on is
approximately 500 ns.
Bits 31 to 24 of the Edge Interrupt Count register define the minimum interval between two
interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to
these bits determines the normal IRQ generation, without any delay. When a delay is
programmed and the IRQ becomes active after the respective delay, several IRQ events
may have already occurred.
All the interrupt events are represented by the respective bits allocated in the Interrupt
register. There is no mechanism to show the order or the moment of occurrence of an
interrupt.
The asserted bits in the Interrupt register can be cleared by writing back the same value to
the Interrupt register. This means that writing logic 1 to each of the set bits will reset the
corresponding bits to the initial inactive state.
The IRQ generation rules that apply according to the preceding settings are:
1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register.
2. Define the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control
3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW
4. Program the individual interrupt enable bits in the Interrupt Enable register. The
– Enable ENABLE_DMA (bit 1) of the DMA Configuration register to determine the
register.
Mode Control register. These settings must match the IRQ settings of the host
processor.
By default, interrupt is level-triggered and active LOW.
software will need to clear the interrupt status bits in the Interrupt register before
enabling individual interrupt enable bits.
assertion of DREQ immediately after setting the bit.
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
© NXP B.V. 2008. All rights reserved.
ISP1760
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