ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
If an event of interrupt occurs but the respective bit in the Interrupt Enable register is
not set, then the respective Interrupt register bit is set but the interrupt signal is not
asserted.
An interrupt will be generated when interrupt is enabled and the respective bit in the
Interrupt Enable register is set.
For a level trigger, an interrupt signal remains asserted until the processor clears the
Interrupt register by writing logic 1 to clear the Interrupt register bits that are set.
If an interrupt is made edge-sensitive and is asserted, writing to clear the Interrupt
register will not have any effect because the interrupt will be asserted for a prescribed
amount of clock cycles.
The clock stopping mechanism does not affect the generation of an interrupt. This is
useful during the suspend and resume cycles, when an interrupt is generated to
signal a wake-up event.
The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ
Mask AND registers.
With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer
(ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will
be generated when the AND or OR conditions are met. The PTDs that are set will wait
until the respective bits of the remaining PTDs are set and then all PTDs generate an
interrupt request to the CPU together.
The registers definition shows that the AND or OR conditions are applicable to the same
category of PTDs: ISO, INT, ATL.
When an IRQ is generated, the PTD Done Map registers and the respective V bits will
show which PTDs were completed.
The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:
The OR mask has a higher priority over the AND mask. An IRQ is generated if bit n of
the done map is set and the corresponding bit n of the OR Mask register is set.
If the OR mask for any done bit is not set, then the AND mask comes into picture. An
IRQ is generated if all the corresponding done bits of the AND Mask register are set.
For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated
only if bits 2, 4, 10 of the done map are set.
If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the
regular time interval as programmed in the ATL Done Timeout register. Even if an
interrupt event occurs before the time-out of the register, no IRQ will be generated
until the time is up.
For an example on using the IRQ Mask AND or IRQ Mask OR registers without the ATL
Done Timeout register, see
The AND function: Activate the IRQ only if PTDs 1, 2 and 4 are done.
The OR function: If any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be
raised.
ISP1760_4
Product data sheet
Embedded Hi-Speed USB host controller
Table
5.
Rev. 04 — 4 February 2008
ISP1760
© NXP B.V. 2008. All rights reserved.
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