ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 5.
PTD
1
2
3
4
5
6
7
8
9
7.5 Phase-Locked Loop (PLL) clock multiplier
The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz
clock already existing in the system with a precision better than 50 ppm. This allows the
use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI).
When an external crystal is used, make sure the CLKIN pin is connected to V
The PLL block generates all the main internal clocks required for normal functionality of
various blocks: 30 MHz, 48 MHz and 60 MHz.
No external components are required for the PLL operation.
7.6 Power management
The ISP1760 implements a flexible power management scheme, allowing various power
saving stages.
The usual powering scheme implies programming EHCI registers and the internal
Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed
USB host controller with a Hi-Speed USB hub attached.
When the ISP1760 is in suspend mode, the main internal clocks will be stopped to ensure
minimum power consumption. An internal LazyClock of 100 kHz
running. This allows initiating a resume on one of these events:
External USB device connect or disconnect
CS_N signal asserted when the ISP1760 is accessed
Driving the SUSPEND/WAKEUP_N pin to a LOW level
The SUSPEND/WAKEUP_N pin is a bidirectional pin. This pin must be connected to one
of the GPIO pins of a processor.
The awake state can be verified by reading the LOW level of this pin. If the level is HIGH,
it means that the ISP1760 is in the suspend state.
The SUSPEND/WAKEUP_N pin requires a pull-up because in the ISP1760 suspended
state the pin becomes 3-state and can be pulled down, driving it externally by switching
the processor’s GPIO line to output mode to generate the ISP1760 wake-up.
ISP1760_4
Product data sheet
Using the IRQ Mask AND or IRQ Mask OR registers
AND register
OR register
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
Time
PTD done
IRQ
1 ms
1
-
-
1
-
-
-
-
3 ms
1
active because of AND
-
-
-
-
-
-
5 ms
1
active because of OR
6 ms
1
active because of OR
7 ms
1
active because of OR
40 % will continue
ISP1760
.
CC(I/O)
© NXP B.V. 2008. All rights reserved.
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