ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 8.
Address
0344h
0354h
0374h
Interrupt registers
0310h
0314h
0318h
031Ch
0320h
0324h
0328h
032Ch
8.1 EHCI capability registers
8.1.1 CAPLENGTH register
The bit description of the Capability Length (CAPLENGTH) register is given in
Table 9.
CAPLENGTH - Capability Length register (address 0000h) bit description
Bit
Symbol
Access Value
7 to 0
CAPLENGTH[7:0] R
8.1.2 HCIVERSION register
Table 10
(HCIVERSION) register.
Table 10.
HCIVERSION - Host Controller Interface Version Number register (address 0002h) bit description
Bit
Symbol
15 to 0
HCIVERSION[15:0] R
8.1.3 HCSPARAMS register
The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that
are structural parameters. The bit allocation is given in
Table 11.
HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit allocation
Bit
31
Symbol
Reset
0
Access
R
ISP1760_4
Product data sheet
Register overview
…continued
Register
DMA Start Address
Power Down Control
Port 1 Control
Interrupt
Interrupt Enable
ISO IRQ Mask OR
INT IRQ Mask OR
ATL IRQ Mask OR
ISO IRQ Mask AND
INT IRQ Mask AND
ATL IRQ Mask AND
Description
20h
Capability Length: This is used as an offset. It is added to the register
base to find the beginning of the operational register space.
shows the bit description of the Host Controller Interface Version Number
Access Value
Description
0100h
Host Controller Interface Version Number: It contains a BCD
encoding of the version number of the interface to which the host
controller interface conforms.
30
29
28
reserved
0
0
0
R
R
R
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
Reset value
References
0000 0000h
Section 8.3.10 on page 47
03E8 1BA0h
Section 8.3.11 on page 48
0086 0086h
Section 8.3.12 on page 50
0000 0000h
Section 8.4.1 on page 51
0000 0000h
Section 8.4.2 on page 53
0000 0000h
Section 8.4.3 on page 54
0000 0000h
Section 8.4.4 on page 55
0000 0000h
Section 8.4.5 on page 55
0000 0000h
Section 8.4.6 on page 55
0000 0000h
Section 8.4.7 on page 55
0000 0000h
Section 8.4.8 on page 56
Table
11.
27
26
25
0
0
0
R
R
R
© NXP B.V. 2008. All rights reserved.
Table
9.
24
0
R
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