ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 

Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 15.
USBCMD - USB Command register (address 0020h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
Bit
7
Symbol
LHCR
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
Table 16.
Bit
31 to 8
7
6 to 2
1
0
[1]
For details on register bit description, refer to
Universal Serial Bus Rev.
8.2.2 USBSTS register
The USB Status (USBSTS) register indicates pending interrupts and various states of the
host controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears register bits by writing ones to them. The bit allocation is
given in
Table 17.
USBSTS - USB Status register (address 0024h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
ISP1760_4
Product data sheet
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
reserved
0
0
0
R/W
R/W
14
13
12
reserved
0
0
0
R/W
R/W
6
5
4
[1]
reserved
0
0
0
R/W
R/W
USBCMD - USB Command register (address 0020h) bit description
[1]
Symbol
Description
-
reserved
LHCR
Light Host Controller Reset (optional): If implemented, it allows the
driver software to reset the EHCI controller without affecting the state of
the ports or the relationship to the companion host controllers. If not
implemented, a read of this field will always return logic 0.
-
reserved
HCRESET Host Controller Reset: This control bit is used by the software to reset
the host controller.
RS
Run/Stop: 1 = Run, 0 = Stop. When set, the host controller executes the
schedule.
1.0”.
Table
17.
30
29
28
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
27
26
25
[1]
0
0
0
R/W
R/W
R/W
19
18
17
[1]
1
0
0
R/W
R/W
R/W
11
10
9
[1]
1
0
1
R/W
R/W
R/W
3
2
1
HCRESET
0
0
0
R/W
R/W
R/W
Ref. 2 “Enhanced Host Controller Interface Specification for
27
26
25
[1]
0
0
0
R/W
R/W
R/W
ISP1760
24
0
R/W
16
0
R/W
8
1
R/W
0
RS
0
R/W
24
0
R/W
© NXP B.V. 2008. All rights reserved.
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