ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 

Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
[1]
Symbol
reserved
Reset
0
Access
R/W
R/W
Bit
7
Symbol
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
Table 20.
Bit
31 to 14
13 to 0
[1]
For details on register bit description, refer to
Universal Serial Bus Rev.
8.2.5 CONFIGFLAG register
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Table 21.
CONFIGFLAG - Configure Flag register (address 0060h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
Bit
7
Symbol
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
ISP1760_4
Product data sheet
22
21
20
reserved
0
0
0
R/W
R/W
14
13
12
0
0
0
R/W
R/W
6
5
4
FRINDEX[7:0]
0
0
0
R/W
R/W
FRINDEX - Frame Index register (address: 002Ch) bit description
[1]
Symbol
Description
-
reserved
FRINDEX
Frame Index: Bits in this register are used for the frame number in the SOF
[13:0]
packet and as the index into the frame list. The value in this register
increments at the end of each time frame. For example, microframe.
1.0”.
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
reserved
0
0
0
R/W
R/W
14
13
12
reserved
0
0
0
R/W
R/W
6
5
4
[1]
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
19
18
17
[1]
0
0
0
R/W
R/W
R/W
11
10
9
FRINDEX[13:8]
0
0
0
R/W
R/W
R/W
3
2
1
0
0
0
R/W
R/W
R/W
Ref. 2 “Enhanced Host Controller Interface Specification for
27
26
25
[1]
0
0
0
R/W
R/W
R/W
19
18
17
[1]
0
0
0
R/W
R/W
R/W
11
10
9
[1]
0
0
0
R/W
R/W
R/W
3
2
1
0
0
0
R/W
R/W
R/W
ISP1760
16
0
R/W
8
0
R/W
0
0
R/W
Table
21.
24
0
R/W
16
0
R/W
8
0
R/W
0
CF
0
R/W
© NXP B.V. 2008. All rights reserved.
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