ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 22.
Bit
31 to 1
0
[1]
For details on register bit description, refer to
Universal Serial Bus Rev.
8.2.6 PORTSC1 register
The Port Status and Control (PORTSC) register (bit allocation:
well. It is reset by hardware only when the auxiliary power is initially applied or in response
to a host controller reset. The initial conditions of a port are:
No peripheral connected
Port disabled
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until the power is
stable on the port (maximum delay is 20 ms from the transition).
Table 23.
PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
PIC[1:0]
Reset
0
Access
R
Bit
7
Symbol
SUSP
FPR
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
ISP1760_4
Product data sheet
CONFIGFLAG - Configure Flag register (address 0060h) bit description
[1]
Symbol
Description
-
reserved
CF
Configure Flag: The host software sets this bit as the last action when it is
configuring the host controller. This bit controls the default port-routing
control logic.
1.0”.
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
[1]
reserved
0
0
0
R/W
R/W
14
13
12
PO
PP
0
1
0
R
R/W
R/W
6
5
4
[1]
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
Ref. 2 “Enhanced Host Controller Interface Specification for
Table
23) is in the power
27
26
25
[1]
0
0
0
R/W
R/W
R/W
19
18
17
PTC[3:0]
0
0
0
R/W
R/W
R/W
11
10
9
LS[1:0]
reserved
0
0
0
R/W
R/W
R/W
3
2
1
PED
ECSC
0
0
0
R/W
R/W
R/W
ISP1760
24
0
R/W
16
0
R/W
8
[1]
PR
0
R
0
ECCS
0
R
© NXP B.V. 2008. All rights reserved.
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