ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 41

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 33.
Table 34.
[1]
ISP1760_4
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
ATL_PTD_LAST
_PTD[31:0]
ATL PTD Last PTD register (address 0158h) bit description
HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation
ANA_DIGI_
8.2.15 ATL PTD Last PTD register
ALL_ATX_
reserved
8.3.1 HW Mode Control register
RESET
R/W
R/W
R/W
R/W
8.3 Configuration registers
OC
31
23
15
0
0
0
7
0
The bit description of the ATL PTD Last PTD register is given in
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed
(checking V = 1) in that PTD category. Subsequently, the process will restart with the first
PTD of that group. This is useful to reduce the time in which all the PTDs, the respective
memory space, would be checked, especially if only a few PTDs are defined. The
LastPTD bit must normally be set to a higher position than any other position indicated by
the NextPTDPointer from an active PTD.
Table 34
Access Value
R/W
DACK_
POL
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
shows the bit allocation of the register.
0000 0000h ATL PTD Last PTD: Last PTD of the 32 PTDs as indicated by the 32
DREQ_
R/W
R/W
R/W
POL
R/W
29
21
13
0
0
0
5
0
Rev. 04 — 4 February 2008
Description
bitmap.
1h — One PTD in ATL
2h — Two PTDs in ATL
4h — Three PTDs in ATL
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
[1]
INTR_POL
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Table
LEVEL
INTR_
R/W
R/W
R/W
R/W
25
17
33.
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1760
DATA_BUS
GLOBAL_
INTR_EN
_WIDTH
R/W
R/W
R/W
R/W
40 of 110
24
16
0
0
8
1
0
0