ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 

Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 35.
Bit
31
30 to 16
15
14 to 9
8
7
6
5
4 to 3
2
1
0
8.3.2 Chip ID register
Read this register to get the ID of the ISP1760. The upper word of the register contains
the hardware version number and the lower word contains the chip ID.
bit description of the register.
ISP1760_4
Product data sheet
HW Mode Control - Hardware Mode Control register (address 0300h) bit
description
Symbol
Description
ALL_ATX_RESET
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset
-
reserved; write logic 0
ANA_DIGI_OC
Analog Digital Overcurrent: This bit selects analog or digital
overcurrent detection on pins OC1_N, OC2_N and OC3_N.
0 — Digital overcurrent
1 — Analog overcurrent
-
reserved; write logic 0
DATA_BUS_WIDTH
Data Bus Width:
0 — Defines a 16-bit data bus width
1 — Sets a 32-bit data bus width
-
reserved; write logic 0
DACK_POL
DACK Polarity:
1 — Indicates that the DACK input is active HIGH
0 — Indicates active LOW
DREQ_POL
DREQ Polarity:
1 — Indicates that the DREQ output is active HIGH
0 — Indicates active LOW
-
reserved; write logic 0
INTR_POL
Interrupt Polarity:
0 — Active LOW
1 — Active HIGH
INTR_LEVEL
Interrupt Level:
0 — INT is level triggered.
1 — INT is edge triggered. A pulse of certain width is generated.
GLOBAL_INTR_EN
Global Interrupt Enable: This bit must be set to logic 1 to
enable the IRQ signal assertion.
0 — IRQ assertion is disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 — IRQ assertion is enabled. IRQ will be asserted according to
the Interrupt Enable register, and events setting and occurrence.
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
Table 36
© NXP B.V. 2008. All rights reserved.
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