ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 39.
Bit
31 to 2
1
0
8.3.5 DMA Configuration register
The bit allocation of the DMA Configuration register is given in
Table 40.
DMA Configuration register (address 0330h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
Bit
7
Symbol
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
ISP1760_4
Product data sheet
SW Reset - Software Reset register (address 030Ch) bit description
Symbol
Description
-
reserved; write logic 0
RESET_HC Reset Host Controller: Reset only the host controller-specific registers
(only registers with address below 300h).
0 — No reset
1 — Enable reset
RESET_ALL Reset All: Reset all the host controller and CPU interface registers.
0 — No reset
1 — Enable reset
30
29
28
DMA_COUNTER[23:16]
0
0
0
R/W
R/W
22
21
20
DMA_COUNTER[15:8]
0
0
0
R/W
R/W
14
13
12
DMA_COUNTER[7:0]
0
0
0
R/W
R/W
6
5
4
[1]
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
Table
40.
27
26
25
0
0
0
R/W
R/W
R/W
19
18
17
0
0
0
R/W
R/W
R/W
11
10
9
0
0
0
R/W
R/W
R/W
3
2
1
BURST_LEN[1:0]
ENABLE_
DMA
0
0
0
R/W
R/W
R/W
© NXP B.V. 2008. All rights reserved.
24
0
R/W
16
0
R/W
8
0
R/W
0
DMA_READ
_WRITE_
SEL
0
R/W
43 of 110