ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 41.
Bit
31 to 8
7 to 4
3 to 2
1
0
8.3.6 Buffer Status register
The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is,
ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets
the Buffer Filled bit of a particular transfer in the Buffer Status register, the HC will start
traversing through PTD headers that are not marked for skipping and are valid PTDs.
Remark: Software can set these bits during the initialization.
Table 42
Table 42.
Buffer Status register (address 0334h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
ISP1760_4
Product data sheet
DMA Configuration register (address 0330h) bit description
Symbol
Description
DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or
write).
Remark: Different number of bursts will be generated for the
same transfer length programmed in 16-bit and 32-bit modes
because DMA_COUNTER is in number of bytes.
-
reserved
BURST_LEN[1:0]
DMA Burst Length:
00 — Single DMA burst
01 — 4-cycle DMA burst
10 — 8-cycle DMA burst
11 — 16-cycle DMA burst
ENABLE_DMA
Enable DMA:
0 — Terminate DMA
1 — Enable DMA
DMA_READ_WRITE_
DMA Read/Write Select: Indicates if the DMA operation is a
SEL
write or read to or from the ISP1760.
0 — DMA write to the ISP1760 internal RAM is set
1 — DMA read from the ISP1760 internal RAM
shows the bit allocation of the Buffer Status register.
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
reserved
0
0
0
R/W
R/W
14
13
12
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
27
26
25
[1]
0
0
0
R/W
R/W
R/W
19
18
17
[1]
0
0
0
R/W
R/W
R/W
11
10
9
[1]
0
0
0
R/W
R/W
R/W
© NXP B.V. 2008. All rights reserved.
24
0
R/W
16
0
R/W
8
0
R/W
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