ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 50.
Bit
31 to 16
15 to 0
8.3.11 Power Down Control register
This register is used to turn off power to the internal blocks of the ISP1760 to obtain
maximum power savings.
Table 51.
Power Down Control register (address 0354h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
1
Access
R/W
R/W
Bit
15
14
Symbol
reserved
Reset
0
Access
R/W
R/W
Bit
7
[1]
Symbol
reserved
Reset
1
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
ISP1760_4
Product data sheet
DMA Start Address register (address 0344h) bit description
Symbol
Description
-
reserved
START_ADDR
Start Address for DMA: The start address for DMA read or write
_DMA[15:0]
cycles.
Table 51
shows the bit allocation of the register.
30
29
28
CLK_OFF_COUNTER[15:8]
0
0
0
R/W
R/W
22
21
20
CLK_OFF_COUNTER[7:0]
1
1
0
R/W
R/W
13
12
[1]
PORT3_
PD
0
0
1
R/W
R/W
6
5
4
BIASEN
VREG_ON
0
1
0
R/W
R/W
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
27
26
0
0
R/W
R/W
R/W
19
18
1
0
R/W
R/W
R/W
11
10
PORT2_
VBATDET_
PD
PWR
1
0
R/W
R/W
R/W
3
2
1
OC3_PWR OC2_PWR OC1_PWR
0
0
0
R/W
R/W
R/W
ISP1760
25
24
1
1
R/W
17
16
0
0
R/W
9
8
[1]
reserved
1
1
R/W
0
HC_CLK_EN
0
R/W
© NXP B.V. 2008. All rights reserved.
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