ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
5. Block diagram
37 to 39, 41 to 43,
45 to 47, 49, 51,
52, 54, 56 to 58,
60 to 62, 64 to 66,
68 to 70, 72 to 74,
76 to 78, 80
DATA[15:0]/DATA[31:0]
82, 84, 86, 87,
89, 91 to 93,
95 to 98,
100 to 103, 105
17
A[17:1]
106
CS_N
107
RD_N
108
WR_N
112
IRQ
114
DREQ
DACK
116
USB FULL-SPEED AND LOW-SPEED DATA PATH
PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS
HI-SPEED
USB ATX1
16
21 127
15
20
19
18
DP1
RREF1
DM1
GND
GNDA
OC1_N
(RREF1)
PSW1_N
The figure shows the LQFP pinout. For the TFBGA ballout, see
All ground pins should normally be connected to a common ground plane.
Fig 1.
Block diagram
ISP1760_4
Product data sheet
V
CC(I/O)
10, 40, 48, 59, 67,
75, 83, 94, 104, 115
ISP1760BE
HC PTD MEMORY
RISC PROCESSOR
(3 kB)
16-bit
INTERFACE:
or
32-bit
HC PAYLOAD
MEMORY
MEMORY (60 kB)
MANAGEMENT
UNIT
+
INTERRUPT
CONTROL
+
MEMORY
SLAVE DMA
ARBITER
CONTROLLER
AND FIFO
+
HARDWARE
CONFIGURATION
REGISTERS
EHCI AND
OPERATIONAL
REGISTERS
TRANSACTION
TRANSLATOR
AND RAM
USB HIGH-SPEED DATA PATH
HI-SPEED
USB ATX2
23
27
28 128
30
22
26
25
DP2
DM2
RREF3
RREF2
GNDA
GND
OC2_N
(RREF3)
(RREF2)
PSW2_N
Table
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
PLL
30 MHz
60 MHz
GLOBAL CONTROL
AND POWER
MANAGEMENT
POWER-ON RESET
AND V
ON
BAT
5, 50,
85, 118
5 V-TO-1.8 V
VOLTAGE
REGULATOR
5 V-TO-3.3 V
PIE
VOLTAGE
REGULATOR
DIGITAL
AND ANALOG
OVERCURRENT
DETECTION
4, 17, 24,
HI-SPEED
31, 123
USB ATX3
53, 88, 121
14, 36, 44, 55, 63,
71, 79, 90, 99, 109
35 1
29
34 33
32
004aaa435
GNDD
DP3
DM3
OC3_N
GND
GNDA
PSW3_N
2.
© NXP B.V. 2008. All rights reserved.
ISP1760
11
XTAL1
12
XTAL2
13
CLKIN
122
RESET_N
119
SUSPEND/
WAKEUP_N
110
BAT_ON_N
REG1V8
6, 7
V
CC(5V0)
9
REG3V3
2
REF5V
8
GND(OSC)
GNDA
GNDC
4 of 110