ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 52.
[1]
Bit
31 to 16 CLK_OFF_
15 to 13 -
12
11
10
9 to 6
5
4
3
ISP1760_4
Product data sheet
Power Down Control register (address 0354h) bit description
Symbol
Description
Clock Off Counter: Determines the wake-up status duration after any
COUNTER
wake-up event before the ISP1760 goes back into suspend mode. This
[15:0]
time-out is applicable only if, during the given interval, the host controller is
not programmed back to the normal functionality.
03E8h — The default value. It determines the default wake-up interval of
10 ms. A value of zero implies that the host controller never wakes up on
any of the events. This may be useful when using the ISP1760 as a
peripheral to save power by permanently programming the host controller
in suspend.
FFFFh — The maximum value. It determines a maximum wake-up time of
500 ms.
The setting of this register is based on the 100 kHz
frequency. It is a multiple of 10 s period.
Remark: In 16-bit mode, the default value is 17E8h. A write operation to
these bits with any value fixes the clock off counter at 1400h. This value is
equivalent to a fixed wake-up time of 50 ms.
reserved
PORT3_PD Port 3 Pull-Down: Controls port 3 pull-down resistors.
0 — Port 3 internal pull-down resistors are not connected.
1 — Port 3 internal pull-down resistors are connected.
PORT2_PD Port 2 Pull-Down: Controls port 2 pull-down resistors.
0 — Port 2 internal pull-down resistors are not connected.
1 — Port 2 internal pull-down resistors are connected.
VBATDET_
V
Detector Powered: Controls the power to the V
BAT
PWR
0 — V
detector is powered or enabled in suspend.
BAT
1 — V
detector is not powered or disabled in suspend.
BAT
-
reserved; write reset value
BIASEN
Bias Circuits Powered: Controls the power to internal bias circuits.
0 — Internal bias circuits are not powered in suspend.
1 — Internal bias circuits are powered in suspend.
VREG_ON
V
Powered: Enables or disables the internal 3.3 V and 1.8 V
REG
regulators when the
0 — Internal regulators are normally powered in suspend.
1 — Internal regulators switch to low power mode (in suspend mode).
OC3_PWR
OC3_N Powered: Controls the powering of the overcurrent detection
circuitry for port 3.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in
standby.
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
40 % LazyClock
BAT
ISP1760
is in suspend.
ISP1760
detector.
© NXP B.V. 2008. All rights reserved.
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