ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 52

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 55.
[1]
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Interrupt register (address 0310h) bit allocation
INT_IRQ
8.4.1 Interrupt register
R/W
R/W
R/W
R/W
8.4 Interrupt registers
31
23
15
0
0
0
7
0
Table 54.
[1]
The bits of this register indicate the interrupt source, defining the events that determined
the INT generation. Clearing the bits that were set because of the events listed is done by
writing back logic 1 to the respective position. All bits must be reset before enabling new
interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN
in the HW Mode Control register.
Bit
31 to 24 -
23
22 to 8
7
6 to 5
4 to 3
2 to 0
[1]
For correct port 1 initialization, write 0080 0018h to this register after power-on.
READY
R/W
R/W
R/W
CLK
R/W
30
22
14
0
0
0
6
0
Symbol
PORT1_INIT2
-
PORT1_INIT1
-
PORT1_POWER
[1:0]
-
Port 1 Control register (address 0374h) bit description
HC_SUSP
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 04 — 4 February 2008
reserved
Description
reserved; write reset value
Port 1 Initialization 2: Write logic 1 at the ISP1760 initialization. It
will clear both this bit and bit 7. Affects only port 1.
reserved
Port 1 Initialization 1: Must be reset to logic 0 at power-up
initialization for correct operation of port 1. Correct host controller
functionality is not ensured if set to logic 1 (affects only port 1). To
clear this bit, logic 1 must be written to bit 23 during the ISP1760
initialization.
This is not required for the normal functionality of port 2 and port 3.
reserved
Port 1 Power: Set these bits to 11b. These bits must be set to enable
port 1 power.
reserved; write reset value
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
Table 55
reserved
reserved
[1]
DMAEOT
shows the bit allocation of the Interrupt register.
[1]
[1]
R/W
R/W
R/W
R/W
INT
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
reserved
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
[1]
SOFITLINT
ISO_IRQ
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1760
reserved
ATL_IRQ
R/W
R/W
R/W
R/W
51 of 110
24
16
0
0
8
0
0
0
[1]