ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 57

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 63.
Table 64.
9. Philips Transfer Descriptor (PTD)
ISP1760_4
Product data sheet
Bit
31 to 0
Bit
31 to 0
Symbol
INT_IRQ_MASK
_AND[31:0]
Symbol
ATL_IRQ_MASK
_AND[31:0]
INT IRQ Mask AND register (address 0328h) bit description
ATL IRQ Mask AND register (address 032Ch) bit description
8.4.8 ATL IRQ Mask AND register
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 64
The standard EHCI data structures as described in
Interface Specification for Universal Serial Bus Rev. 1.0”
operation that is managed by the hardware state machine.
The PTD structures of the ISP1760 are translations of the EHCI data structures that are
optimized for the ISP1760. It, however, still follows the basic EHCI architecture. This
optimized form of EHCI data structures is necessary because the ISP1760 is a slave host
controller and has no bus master capability.
EHCI manages schedules in two lists: periodic and asynchronous. The data structures
are designed to provide the maximum flexibility required by USB, minimize memory traffic,
and reduce hardware and software complexity. The ISP1760 controller executes
transactions for devices by using a simple shared-memory schedule. This schedule
consists of data structures organized into three lists.
qISO — Isochronous transfer
qINTL — Interrupt transfer
qATL — Asynchronous transfer; for the control and bulk transfers
The system software maintains two lists for the host controller: periodic and
asynchronous.
The ISP1760 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are
used as channels to transfer data from the shared memory to the USB bus. These
channels are allocated and de-allocated on receiving the transfer from the core USB
driver.
Access
R/W
Access
R/W
shows the bit description of the register.
Value
0000 0000h INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.
Value
0000 0000h ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.
Rev. 04 — 4 February 2008
Description
0 — No OR condition defined between INT PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
0 — No OR condition defined between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 ATL PTDs.
Embedded Hi-Speed USB host controller
Ref. 2 “Enhanced Host Controller
are optimized for the bus master
Section
7.4.
© NXP B.V. 2008. All rights reserved.
ISP1760
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