ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 96.
T
= 40 C to +85 C; unless otherwise specified.
amb
Symbol
t
d23
t
w13
t
su13
t
su23
14.2 DMA timing
In the following sections:
Polarity of DACK is active HIGH
Polarity of DREQ is active HIGH.
14.2.1 Single cycle: DMA read
Fig 19. DMA read (single cycle)
Table 97.
T
= 40 C to +85 C; unless otherwise specified.
amb
Symbol
V
= 1.65 V to 1.95 V
CC(I/O)
t
a14
t
a24
t
d14
t
w14
t
a34
t
a44
t
h14
V
= 3.3 V to 3.6 V
CC(I/O)
t
a14
t
a24
t
d14
ISP1760_4
Product data sheet
Memory read
…continued
Parameter
data available time after RD_N HIGH
RD_N pulse width
CS_N set-up time before RD_N LOW
address set-up time before RD_N LOW
DREQ
t
t
a14
a34
DACK
t
w14
RD_N
t
d14
t
a24
DATA
DMA read (single cycle)
Parameter
DACK assertion time after DREQ assertion
RD_N assertion time after DACK assertion
data valid time after RD_N assertion
RD_N pulse width
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
DACK assertion time after DREQ assertion
RD_N assertion time after DACK assertion
data valid time after RD_N assertion
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
Min
Max
-
1
21
-
0
-
0
-
t
a44
t
h14
004aaa530
Min
Max
0
-
0
-
-
24
> t
-
d14
-
29
56
-
5
0
-
0
-
-
20
© NXP B.V. 2008. All rights reserved.
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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