ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 97.
T
= 40 C to +85 C; unless otherwise specified.
amb
Symbol
t
w14
t
a34
t
a44
t
h14
14.2.2 Single cycle: DMA write
Fig 20. DMA write (single cycle)
Table 98.
T
= 40 C to +85 C; unless otherwise specified.
amb
Symbol Parameter
V
= 1.65 V to 1.95 V
CC(I/O)
t
a15
t
a25
t
h15
t
h25
t
su15
t
a35
t
cy15
t
w15
V
= 3.3 V to 3.6 V
CC(I/O)
t
a15
t
a25
t
h15
t
h25
t
su15
t
a35
t
cy15
t
w15
ISP1760_4
Product data sheet
DMA read (single cycle)
…continued
Parameter
RD_N pulse width
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
DREQ
t
a15
t
a35
DACK
t
w15
t
a25
WR_N
t
su15
DATA
data
DREQ and DACK are active HIGH.
DMA write (single cycle)
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
Min
Max
> t
-
d14
-
18
56
-
5
t
cy15
t
h25
t
h15
data 1
004aaa525
Min
Max
0
-
1
-
3
-
0
-
5.5
-
-
28
-
82
22
-
0
-
1
-
2
-
0
-
5.5
-
-
16
-
82
22
-
© NXP B.V. 2008. All rights reserved.
Unit
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ns
Unit
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ns
ns
ns
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