ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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Page 97/111

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NXP Semiconductors
14.2.4 Multi-cycle: DMA write
Fig 22. DMA write (multi-cycle burst)
Table 100. DMA write (multi-cycle burst)
T
= 40 C to +85 C; unless otherwise specified.
amb
Symbol Parameter
V
= 1.65 V to 1.95 V
CC(I/O)
T
cy17
t
su17
t
h17
t
a17
t
a27
t
a37
t
h27
t
a47
t
w17
t
a57
V
= 3.3 V to 3.6 V
CC(I/O)
T
cy17
t
su17
t
h17
t
a17
t
a27
t
a37
t
h27
t
a47
t
w17
t
a57
ISP1760_4
Product data sheet
DREQ
t
a17
DACK
t
T
su17
WR_N
t
a47
t
a27
t
h17
DATA
data 1
DMA write cycle time
data set-up time before WR_N de-assertion
data hold time after WR_N de-assertion
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
DREQ de-assertion time at last strobe (WR_N)
assertion
DACK hold time after WR_N de-assertion
strobe de-assertion to next strobe assertion time
WR_N pulse width
DACK de-assertion to next DREQ assertion time
DMA write cycle time
data set-up time before WR_N de-assertion
data hold time after WR_N de-assertion
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
DREQ de-assertion time at last strobe (WR_N)
assertion
DACK hold time after WR_N de-assertion
strobe de-assertion to next strobe assertion time
WR_N pulse width
DACK de-assertion to next DREQ assertion time
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
t
a57
t
t
a37
cy17
t
w17
data n-1
data 2
data n
004aaa526
Min
Max
51
-
5
-
2
-
0
-
2
-
-
28
0
-
34
-
17
-
-
82
51
-
5
-
2
-
0
-
1
-
-
16
0
-
34
-
17
-
-
82
© NXP B.V. 2008. All rights reserved.
ISP1760
h27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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