NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet
NH82801FBM S L89K
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... Intel I/O Controller Hub 6 (ICH6) Family Datasheet ® For the Intel 82801FB ICH6, 82801FR ICH6R and 82801FBM ICH6-M I/O Controller Hubs January 2005 Document Number: 301473-002 ...
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... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...
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... System Management Interface........................................................................................... 68 2.16 Real Time Clock Interface ..................................................................................................69 2.17 Other Clocks ....................................................................................................................... 69 2.18 Miscellaneous Signals ........................................................................................................ 69 ® 2.19 AC ’97/Intel High Definition Audio Link ............................................................................. 70 2.20 General Purpose I/O ...........................................................................................................71 2.21 Power and Ground.............................................................................................................. 73 2.22 Pin Straps ........................................................................................................................... 74 2.22.1 Functional Straps ................................................................................................... 74 2.22.2 External RTC Circuitry ........................................................................................... 76 2.22.3 Power Sequencing Requirements ......................................................................... 76 2 ...
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... EEPROM (256x16, 1 MHz).................................................................. 115 5.4.2.3 Legacy Sensor SMBus Devices........................................................... 115 5.4.2.4 Remote Control SMBus Devices ......................................................... 115 5.4.2.5 ASF Sensor SMBus Devices ............................................................... 115 5.4.3 ASF Software Support ......................................................................................... 115 5.5 LPC Bridge (w/ System and Management Functions) (D31:F0)....................................... 116 4 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... SYNC Error Indication..........................................................................119 5.5.1.8 LFRAME# Usage .................................................................................119 5.5.1.9 I/O Cycles ............................................................................................120 5.5.1.10 Bus Master Cycles ...............................................................................120 5.5.1.11 LPC Power Management .....................................................................120 5.5.1.12 Configuration and Intel 5.6 DMA Operation (D31:F0) ..................................................................................................121 5.6.1 Channel Priority ...................................................................................................122 5.6.1.1 Fixed Priority ........................................................................................122 5.6.1.2 Rotating Priority ...
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... Dual-Processor Issues (Desktop Only)................................................................ 149 5.13.2.1 Signal Differences................................................................................ 149 5.13.2.2 Power Management............................................................................. 150 5.14 Power Management (D31:F0) .......................................................................................... 150 5.14.1 Features............................................................................................................... 150 ® 5.14.2 Intel ICH6 and System Power States ................................................................ 151 5.14.3 System Power Planes.......................................................................................... 153 6 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... BATLOW# (Battery Low) (Mobile Only) ...............................................171 5.14.11.7 Controlling Leakage and Power Consumption During Low-Power States ....................................................................172 5.14.12 Clock Generators .................................................................................................172 5.14.12.1 Clock Control Signals from Intel Synthesizer (Mobile Only) ....................................................................173 5.14.13 Legacy Power Management Theory of Operation ...............................................173 5.14.13.1 APM Power Management (Desktop Only) ...........................................173 5 ...
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... Theory of Operation............................................................................................. 186 5.17.1.1 Standard ATA Emulation ..................................................................... 186 5.17.1.2 48-Bit LBA Operation ........................................................................... 187 5.17.2 SATA Swap Bay Support..................................................................................... 187 ® 5.17.3 Intel Matrix Storage Technology Configuration (ICH6R Only) ........................... 187 5.17.3.1 Intel 5.17.4 Power Management Operation............................................................................ 188 5.17.4.1 Power State Mappings......................................................................... 188 5 ...
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... Host Controller .....................................................................................................214 5.21.1.1 Command Protocols ............................................................................215 5.21.2 Bus Arbitration .....................................................................................................218 5.21.3 Bus Timing ...........................................................................................................219 5.21.3.1 Clock Stretching ...................................................................................219 5.21.3.2 Bus Time Out (Intel 5.21.4 Interrupts / SMI# ..................................................................................................220 5.21.5 SMBALERT# .......................................................................................................221 5.21.6 SMBus CRC Generation and Checking...............................................................221 5.21.7 SMBus Slave Interface ........................................................................................221 5 ...
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... AC ’97 Cold Reset ............................................................................................... 233 5.22.5 AC ’97 Warm Reset ............................................................................................. 233 5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec............................... 233 5.23 Intel® High Definition Audio (D27:F0) .............................................................................. 234 5.23.1 Link Protocol Overview ........................................................................................ 234 5.23.1.1 Frame Composition.............................................................................. 234 5.23.2 Link Reset............................................................................................................ 235 5.23.3 Link Power Management ..................................................................................... 235 ...
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... Controller—B1:D8:F0) ................................................................................282 8.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) ................................................................................283 8.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) ................................................................................284 8.1.5 RID—Revision Identification Register (LAN Controller—B1:D8:F0) ................................................................................285 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ..........................................................................281 Contents 11 ...
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... Register (LAN Controller—B1:D8:F0).................................................................. 298 8.2.4 PORT—PORT Interface Register (LAN Controller—B1:D8:F0) ................................................................................ 298 8.2.5 EEPROM_CNTL—EEPROM Control Register (LAN Controller—B1:D8:F0) ................................................................................ 299 8.2.6 MDI_CNTL—Management Data Interface (MDI) Control Register (LAN Controller—B1:D8:F0).................................................................. 300 12 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... PET_SEQ2—PET Sequence 2 Register (ASF Controller—B1:D8:F0) ................................................................................316 8.3.15 STA—Status Register (ASF Controller—B1:D8:F0) ................................................................................317 8.3.16 FOR_ACT—Forced Actions Register (ASF Controller—B1:D8:F0) ................................................................................318 8.3.17 RMCP_SNUM—RMCP Sequence Number Register (ASF Controller—B1:D8:F0) ................................................................................318 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Contents 13 ...
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... Register (PCI-PCI—D30:F0) ............................................................................... 334 9.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI—D30:F0) ............................................................................... 334 9.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .............................. 334 9.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0) .................................. 334 14 ......................................................................... 325 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) ...............................................................................................357 10.1.24 FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0) ...............................................................................................358 10.1.25 FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) ...............................................................................................359 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...................................................................343 Contents 15 ...
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... ELCR1—Master Controller Edge/Level Triggered Register (LPC I/F—D31:F0)............................................................................................... 378 10.4.11 ELCR2—Slave Controller Edge/Level Triggered Register (LPC I/F—D31:F0)............................................................................................... 379 10.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0) ........................................ 380 10.5.1 APIC Register Map (LPC I/F—D31:F0) ............................................................... 380 16 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... Power Management I/O Registers.......................................................................403 10.8.3.1 PM1_STS—Power Management 1 Status Register ............................404 10.8.3.2 PM1_EN—Power Management 1 Enable Register .............................406 10.8.3.3 PM1_CNT—Power Management 1 Control .........................................407 10.8.3.4 PM1_TMR—Power Management 1 Timer Register ............................408 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Contents 17 ...
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... ALT_GP_SMI_EN—Alternate GPI SMI Enable Register..................... 420 10.8.3.15 ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................... 420 10.8.3.16 DEVACT_STS — Device Activity Status Register............................... 421 10.8.3.17 SS_CNT— Intel SpeedStep Control Register (Mobile Only)............................................................. 422 10.8.3.18 C3_RES— C3 Residency Register (Mobile Only) ............................... 422 10 ...
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... When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ...............460 12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)...............................................460 12.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2) ............................................................................460 12.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2) ...................................................................................................461 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ............................................................................455 Contents 19 ...
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... BAR — Legacy Bus Master Base Address Register (SATA–D31:F2) ................................................................................................... 462 12.1.15 ABAR — AHCI Base Address Register (SATA–D31:F2) ................................................................................................... 463 12.1.15.1 Intel 12.1.15.2 Intel 12.1.16 SVID—Subsystem Vendor Identification Register (SATA–D31:F2) ................................................................................................... 463 12.1.17 SID—Subsystem Identification Register (SATA–D31:F2) ................................... 464 12.1.18 CAP— ...
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... RID—Revision Identification Register (USB—D29:F0/F1/F2/F3) ....................................................................................509 13.1.6 PI—Programming Interface Register (USB—D29:F0/F1/F2/F3) ....................................................................................510 13.1.7 SCC—Sub Class Code Register (USB—D29:F0/F1/F2/F3) ....................................................................................510 13.1.8 BCC—Base Class Code Register (USB—D29:F0/F1/F2/F3) ....................................................................................510 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet .............................................................................................507 Contents 21 ...
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... EHCI—D29:F7) .......................................................................................... 531 14.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F7) .......................................................................................... 531 14.1.8 BCC—Base Class Code Register (USB EHCI—D29:F7) .......................................................................................... 531 14.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F7) .......................................................................................... 532 22 ............................................................................. 527 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... Capability Register (USB EHCI—D29:F7) ...........................................................539 14.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F7) ..................................................540 14.1.28 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..........................................................................................541 14.1.29 ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) ..........................................................................................543 14.1.30 USB2IR— ...
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... PEC—Packet Error Check (PEC) Register (SMBus—D31:F3) ............................................................................................... 574 15.2.9 RCV_SLVA—Receive Slave Address Register (SMBus—D31:F3) ............................................................................................... 575 15.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) .......................... 575 15.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ................................... 575 24 ......................................................................... 563 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... PCS—Power Management Control and Status Register (Audio—D30:F2) ..................................................................................................592 16.2 AC ’97 Audio I/O Space (D30:F2).....................................................................................593 16.2.1 x_BDBAR—Buffer Descriptor Base Address Register (Audio—D30:F2) ..................................................................................................596 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet .............................................................581 Contents 25 ...
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... Index Value Register (Modem—D30:F3) ............................................................................................... 620 17.2.7 x_CR—Control Register (Modem—D30:F3) ....................................................... 621 17.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3).................................. 622 17.2.9 GLOB_STA—Global Status Register (Modem—D30:F3) ................................... 623 26 .......................................................... 607 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... High Definition Audio Controller—D27:F0) ...............................................632 18.1.12 HDBARL—Intel ® (Intel High Definition Audio Controller—D27:F0) ...............................................632 18.1.13 HDBARU—Intel ® (Intel High Definition Audio Controller—D27:F0) ...............................................632 18.1.14 SVID—Subsystem Vendor Identification Register ® (Intel High Definition Audio Controller—D27:F0) ...............................................633 18.1.15 SID— ...
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... VCiSTS—VCi Resource Status Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 647 18.1.45 RCCAP—Root Complex Link Declaration Enhanced Capability Header Register (Intel 18.1.46 ESD—Element Self Description Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 648 18.1.47 L1DESC—Link 1 Description Register ® ...
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... CORBRP—CORB Write Pointer Register ® (Intel High Definition Audio Controller—D27:F0) ...............................................660 18.2.17 CORBRP—CORB Read Pointer Register ® (Intel High Definition Audio Controller—D27:F0) ...............................................661 18.2.18 CORBCTL—CORB Control Register ® (Intel High Definition Audio Controller—D27:F0) ...............................................661 18.2.19 CORBST— ...
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... SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register ® (Intel High Definition Audio Controller—D27:F0) ............................................... 674 18.2.42 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel —D27:F0) ............................................................................................................ 674 19 PCI Express* Configuration Registers 19.1 PCI Express* Configuration Registers (PCI Express— ...
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... LCTL—Link Control Register (PCI Express—D28:F0/F1/F2/F3)........................................................................693 19.1.29 LSTS—Link Status Register (PCI Express—D28:F0/F1/F2/F3)........................................................................694 19.1.30 SLCAP—Slot Capabilities Register (PCI Express—D28:F0/F1/F2/F3)........................................................................695 19.1.31 SLCTL—Slot Control Register (PCI Express—D28:F0/F1/F2/F3)........................................................................696 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Contents 31 ...
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... Express—D28:F0/F1/F2/F3) ....................................................................... 708 19.1.55 UEV — Uncorrectable Error Severity (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 709 19.1.56 CES — Correctable Error Status Register (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 710 19.1.57 CEM — Correctable Error Mask Register (PCI Express—D28:F0/F1/F2/F3) ....................................................................... 710 32 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... AC Characteristics ............................................................................................................743 22.5 Timing Diagrams...............................................................................................................759 23 Package Information 24 Testability ...............................................................................................................................779 24.1 XOR Chain Test Mode Description...................................................................................779 24.1.1 XOR Chain Testability Algorithm Example ..........................................................780 24.2 XOR Chain Tables ............................................................................................................781 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ........................................................................715 .................................................................................................733 ..........................................................................................................777 Contents 33 ...
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... AC ’97 2.3 Controller-Codec Connection ................................................................................. 229 5-13 AC-Link Protocol....................................................................................................................... 230 5-14 AC-Link Powerdown Timing ..................................................................................................... 231 5-15 SDIN Wake Signaling ............................................................................................................... 232 ® 5-16 Intel High Definition Audio Link Protocol Example ................................................................. 234 ® 21-1 Intel ICH6 Preliminary Ballout (Topview–Left Side)................................................................ 724 ® ...
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... System Management Interface Signals ...................................................................................... 68 2-16 Real Time Clock Interface .......................................................................................................... 69 2-17 Other Clocks ............................................................................................................................... 69 2-18 Miscellaneous Signals ................................................................................................................ 69 ® 2-19 AC ’97/Intel High Definition Audio Link Signals ........................................................................ 70 2-20 General Purpose I/O Signals ...................................................................................................... 71 2-21 Power and Ground Signals......................................................................................................... 73 2-22 Functional Strap Definitions........................................................................................................ 74 3-1 Integrated Pull-Up and Pull-Down Resistors .............................................................................. 79 3-2 IDE Series Termination Resistors ...
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... Configuration Bits Reset by RTCRST# Assertion .................................................................... 146 5-21 INIT# Going Active ................................................................................................................... 148 5-22 NMI Sources............................................................................................................................. 149 5-23 DP Signal Differences .............................................................................................................. 149 5-24 General Power States for Systems Using Intel 5-25 State Transition Rules for Intel 5-26 System Power Plane ................................................................................................................ 153 5-27 Causes of SMI# and SCI .......................................................................................................... 154 5-28 Break Events (Mobile Only) ...
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... Features Supported by Intel 5-57 Output Tag Slot 0......................................................................................................................231 6-1 PCI Devices and Functions ......................................................................................................238 6-2 Fixed I/O Ranges Decoded by Intel 6-3 Variable I/O Decode Ranges ....................................................................................................242 6-4 Memory Decode Ranges from Processor Perspective.............................................................243 7-1 Chipset Configuration Register Memory Map (Memory Space) ...............................................247 8-1 LAN Controller PCI Register Address Map (LAN Controller— ...
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... Interface Timings .......................................................................................................... 752 22-17SMBus Timing......................................................................................................................... 752 22-19LPC Timing ............................................................................................................................. 753 22-20Miscellaneous Timings............................................................................................................ 753 ® 22-18AC ’97 / Intel High Definition Audio Timing ........................................................................... 753 22-21(Power Sequencing and Reset Signal Timings....................................................................... 754 22-22Power Management Timings .................................................................................................. 756 24-1 XOR Test Pattern Example ...................................................................................................... 780 24-2 XOR Chain #1 (REQ[4:1]# = 0000) .......................................................................................... 781 24-3 XOR Chain #2 (REQ[4:1]# = 0001) ...
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... Initial release. • Added ICH6-M content • Removed support for Wireless SKUs. -002 • Added all specification clarifications, changes and document changes from Specification Updates. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Contents Date June 2004 January 2005 39 ...
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... ACPI 2.0 compliant — ACPI-defined power states (C1, S1, S3–S5 for Desktop and C1-C4, S1, S3–S5 for Mobile) — ACPI Power Management Timer — (Mobile Only) Support for “Intel ® SpeedStep technology” processor power control and “Deeper Sleep” power state — ...
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... Timers to detect improper processor reset — Integrated processor frequency strap logic — Supports ability to disable external devices ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Interrupt Controller — Supports up to eight PCI interrupt pins — Supports PCI 2.3 Message Signaled — ...
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... Definition Audio Codec(s) PCI Express* x1 LAN Connect GPIO Other ASICs (Optional) TPM (Optional) (To (G)MCH) USB 2.0 (Supports 8 USB ports) IDE SATA (2 ports) ® AC ’97/Intel High ® Intel ICH6 Definition Audio Codec(s) PCI Express* x1 LAN Connect GPIO LPC I/F Other ASICs (Optional) TPM (Optional) ® ...
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... Note: Throughout this datasheet, the term “Desktop” refers to any implementation other than mobile desktop, server, workstation, etc., unless specifically noted otherwise. The term “Mobile” refers to implementations using the Intel 82801FBM ICH6 Mobile (ICH6-M). This datasheet assumes a working knowledge of the vocabulary and principles of PCI Express*, ...
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... Device 8, Function 0 (B1:D8:F0). Chapter 9. PCI-to-PCI Bridge Registers Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). 44 Specification ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Location http://www.dmtf.org/standards/asf http://T13.org (T13 1410D) http://www.intel.com/labs/platcomp/hpet/ hpetspec.htm ...
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... Chapter 18. Intel® High Definition Audio Controller Registers Chapter 18 provides a detailed description of all registers that reside in the Intel® High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 19. PCI Express* Port Controller Registers Chapter 19 provides a detailed description of all registers that reside in the PCI Express controller ...
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... Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a., AC ’97 Component Specification, Revision 2.3) which provides a link for Audio and Telephony codecs ( channels) • Supports Intel High Definition Audio • Low Pin Count (LPC) interface • Firmware Hub (FWH) interface support The ICH6 incorporates a variety of PCI functions that are divided into six logical devices (B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8). D30 is the DMI-to-PCI bridge and the AC ’ ...
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... IDE Controller SATA Controller SMBus Controller USB UHCI Controller 1 USB UHCI Controller 2 USB UHCI Controller 3 USB UHCI Controller 4 USB 2.0 EHCI Controller PCI Express* Port 1 PCI Express Port 2 PCI Express Port 3 PCI Express Port 4 Intel High Definition Audio Controller LAN Controller Introduction 47 ...
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... Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). ® AHCI (Intel ICH6R/ICH6-M only) The ICH6R/ICH6-M provide hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices— ...
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... Two large transmit and receive FIFOs each help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Introduction Section 5.19 and Section 5 ...
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... The ICH6 integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. 50 Section 5.3 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet for ...
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... Function Disable. The ICH6 provides the ability to disable the following integrated functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel High Definition Audio, SATA, or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disable functions. • ...
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... Note: Users interested in providing feedback on the Intel High Definition Audio specification or planning to implement the Intel High Definition Audio specification into a future product will need to execute the Intel High Definition Audio Specification Developer’s Agreement. For more information, contact nextgenaudio@intel.com. AC ’ ...
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... The following notations are used to describe the signal type: I Input Pin O Output Pin OD O Open Drain Output Pin Open Drain Input Pin. OD I/O Open Drain Input/Output Pin Open Collector Output Pin. I/O Bi-directional Input / Output Pin. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Signal Description 53 ...
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... Signal Description ® Figure 2-1. Intel ICH6 Interface Signals Block Diagram (Desktop) REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[4]# / GPO[48] GNT[5]# / GPO[17] GNT[6]# / GPO[16] CPUPWRGD / GPO[49] PIRQ[H:E]# / GPIO[5:2] OC[4]# / GPI[9] OC[5]# / GPI[10] OC[6]# / GPI[14] OC[7]# / GPI[15] SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN GPI[41:40, 15:0] ...
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... Figure 2-2. Intel ICH6-M Interface Signals Block Diagram (Mobile Only) REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[4]# / GPO[48] GNT[5]# / GPO[17] GNT[6]# / GPO[16] CPUPWRGD / GPO[49] PIRQ[H:E]# / GPI[5:2] OC[4]# / GPI[9] OC[5]# / GPI[10] OC[6]# / GPI[14] OC[7]# / GPI[15] SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN GPIO[34:33, 28:27, 25:24] ...
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... PCI Express Differential Transmit Pair 2 I PCI Express Differential Receive Pair 2 O PCI Express Differential Transmit Pair 3 I PCI Express Differential Receive Pair 3 O PCI Express Differential Transmit Pair 4 I PCI Express Differential Receive Pair 4 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Description ...
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... LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals are O multiplexed onto this pin. O EEPROM Shift Clock: Serial shift clock output to the EEPROM. EEPROM Data In: Transfers data from the EEPROM to the Intel I has an integrated pull-up resistor. O EEPROM Data Out: Transfers data from the ICH6 to the EEPROM. ...
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... PCI Address/Data: AD[31: multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The Intel AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins ...
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... PCICLK PCIRST# O ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Target Ready: TRDY# indicates the ICH6's ability as a target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. ...
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... Port 3. (Desktop Only) Serial ATA Resistor Bias: These are analog connection points for an external O resistor to ground. Serial ATA Resistor Bias Complement: These are analog connection points I for an external resistor to ground. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Description ...
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... AT compatible DMA channel. There is a weak internal pull- down resistor on this signal. IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the IDE connector. DDACK# is asserted by the Intel O slave devices that a given data transfer cycle (assertion of DIOR# or DIOW DMA data transfer cycle ...
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... LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to external Super I/O device. An internal pull-up resistor is provided on these signals. LDRQ[1]# may optionally be used as GPI. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Description ...
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... PIRQ[H:E GPI[5:2] IDEIRQ ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 10, 11, 12 described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control register. ...
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... USB Resistor Bias: Analog connection point for an external resistor. This O signal is used to set transmit currents and internal load resistors. USB Resistor Bias Complement: Analog connection point for an external I resistor. This signal is used to set transmit currents and internal load resistors. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description ...
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... SYS_RESET# I RSMRST# I ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Platform Reset: The ICH6 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH6 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h) ...
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... C4 state. When the signal is high, the voltage regulator outputs the lower “Deeper Sleep” voltage. When low (default), the voltage regulator outputs the higher “Normal” voltage. Deeper Sleep: This is a copy of the DPRSLPVR and it is active low. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
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... Processor Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. ® The Intel ICH6 can optionally assert the CPUSLP# signal when going to the S1 state, and will always assert it when going C4. ...
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... SMBus Clock signal, and SMLINK1 corresponds to an SMBus Data signal. SMLink Alert: Output of the integrated LAN and input to either the integrated ASF or an external management controller in order for the LAN’s SMLINK slave to be serviced. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description Description Description ...
Page 69
... INTVRMEN SPKR RTCRST# ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Crystal Input 1: This signal is connected to the 32.768 kHz crystal external crystal is used, then RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 kHz crystal external crystal is used, then RTCX2 should be left floating ...
Page 70
... Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode of the shared Intel High Definition Audio/AC ‘97 signals. When set ‘97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode). ...
Page 71
... O GPIO[22] N/A GPO[21] O GPO[20] O (Desktop Only) GPO[19] O ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 1,2 (Sheet Tolerance Power Well This signal is fixed as output only and can instead be V_CPU_IO Core used as CPUPWRGD. This signal is fixed as output only and can instead be 3.3 V Core used as GNT4# ...
Page 72
... Some ICH6 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low Power Button Override event will result in the Intel ICH6 driving a pin to a logic 1 to another device that is powered down. ...
Page 73
... V supply for core well logic (1 pins). This signal is used for the DMI PLL. This power may VccDMIPLL be shut off in S3, S4 states. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description If generated internally, these pins should not be connected to an external supply. ...
Page 74
... This signal has a weak internal pull-up during RSMRST# RSMRST# and is disabled within 100 ms after RSMRST# de-asserts. This signal has a weak internal pull-down. NOTE: This signal should not be pulled high. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Table 2-13. Comment ...
Page 75
... Entrance NOTE: See Section 3.1for full details on pull-up/pull-down resistors. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet When Sampled Signal has a weak internal pull-up. Allows for select memory ranges to be forwarded out the PCI Interface as opposed to the Firmware Hub. When sampled high, Rising Edge of destination is LPC ...
Page 76
... VccSus1_5 or after VccSus1_5 within 0.7 V. VccSus1_5 must power down before VccSus3_3 or after VccSus3_3 within 0 Figure 2-3 Schottky 1 µF Diodes (20% tolerance) 20 KΩ 32.768 kHz Xtal 1.0 µF C1 (20% tolerance (5% tolerance) ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet shows an example schematic VCCRTC RTCX2 R1 10 MΩ RTCX1 (5% tolerance) RTCRST# ...
Page 77
... Vcc1_5 or after Vcc1_5 within 0.7 V. Note: Loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the device ID location, then 266Ch is used. Refer to the ICH6 EEPROM Map and Programming Guide for LAN Device IDs. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Signal Description § 77 ...
Page 78
... Signal Description 78 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 79
... The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set Both Function 2 and Function 3 of Device 30 are disabled. Otherwise, the integrated Pull-down resistor is disabled. 2. The AC ‘97/Intel High Definition Audio Link signals may either all be configured AC-Link or an Intel High Definition Audio Link. ® ...
Page 80
... Otherwise, the integrated Pull-down resistor is disabled. 6. Simulation data shows that these resistor values can range from 10 kΩ kΩ. 7. The pull-down on this signal (in Intel High Definition Audio mode) is only enabled when Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ. ...
Page 81
... GNT[4:0]# GNT[5]# GNT[6]# IRDY#, TRDY# PAR PCIRST# PERR# PLOCK# STOP# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] EE_CS EE_DOUT EE_SHCLK LAN_RSTSYNC LAN_TXD[2:0] ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet During Immediately Power 1 PLTRST# / after PLTRST# Plane 2 RSMRST# RSMRST# PCI Express* Vcc3_3 High High ...
Page 82
... High-Z Power Management VccSus3_3 Low High VccSus3_3 Low High VccSus3_3 Low High VccSus3_3 Low High VccSus3_3 Low High VccSus3_3 Low ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet S4/S5 COLD 2 Undefined Off Off High Off Off High-Z Off Off Low Off ...
Page 83
... High-Z with Vcc3_3 Internal Pull- Low down AC ’97 Interface VccSus3_3 Low Low Vcc3_3 Low Running Vcc3_3 Low Running Intel High Definition Audio Interface VccSus3_3 Low Low High-Z with Vcc3_3 Internal Pull- Running down High-Z with Vcc3_3 Internal Pull- Running down High-Z with ...
Page 84
... CPUPWRGD will be expected to transition from low to High-Z. 8. ICH6 drives these signals Low before PWROK rising and Low after the processor reset. 9. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. ...
Page 85
... Vcc3_3 IRDY#, TRDY# Vcc3_3 PAR Vcc3_3 PCIRST# VccSus3_3 PERR# Vcc3_3 PLOCK# Vcc3_3 STOP# Vcc3_3 LAD[3:0] / Vcc3_3 FWH[3:0] LFRAME# / Vcc3_3 FWH[4] ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet During Immediately 6 6 PLTRST# / after PLTRST# / C3/ RSMRST# RSMRST# PCI Express* 12 High High Defined ...
Page 86
... Low High High Low High High High High Defined High High Low Low High High Low Low Low/High ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet S4/S5 COLD Defined Note 4 Note 4 Defined Note 4 Note 4 Defined Note 4 Note 4 Defined Note 4 Note 4 Defined ...
Page 87
... STPCLK# V_CPU_IO DPSLP# V_CPU_IO SMBCLK, VccSus3_3 SMBDATA SMLINK[1:0] VccSus3_3 LINKALERT# VccSus3_3 SPKR Vcc3_3 ACZ_RST# VccSus3_3 ACZ_SDOUT Vcc3_3 ACZ_SYNC Vcc3_3 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet During Immediately 6 6 PLTRST# / after PLTRST# / C3/ RSMRST# RSMRST# High High Low/High Low Processor Interface ...
Page 88
... GPIO[25] transitions from pulled high internally to actively driven following the de-assertion of the RSMRST# pin. 10.SLP_S5# signals will be high in the S4 state. 11.Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 12.PETp/n[4:1] high until port is enabled by software. ...
Page 89
... Power Well Driver During Reset Vcc3_3 External Microcontroller Vcc3_3 AC ’97 Codec VccSus3_3 AC ’97 Codec Intel High Definition Audio VccSus3_3 Codec Vcc3_3 Clock Generator Vcc3_3 Clock Generator Vcc3_3 IDE Device Vcc3_3 ...
Page 90
... External RC Circuit VccRTC External RC Circuit Vcc3_3 Clock Generator Vcc3_3 SATA Drive Vcc3_3 External Pull-down External Device or External Vcc3_3 Pull-up/Pull-down Vcc3_3 PCI Bus Peripherals ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet S4/S5 COLD Driven Low Low Static Low Low Driven Driven ...
Page 91
... Vcc3_3 Processor Voltage Regulator VccSus3_3 External Pull-up state. HOT Driver During Reset Vcc3_3 External Microcontroller Vcc3_3 AC ’97 Codec AC ’97 Codec Intel High Definition Audio Codec Graphics Component Vcc3_3 [(G)MCH] Power Supply Vcc3_3 Clock Generator Vcc3_3 Clock Generator Vcc3_3 IDE Device Vcc3_3 ...
Page 92
... Internal Pull-up Internal Pull-up VccRTC System Power Supply Vcc3_3 External Microcontroller Vcc3_3 PCI Master Serial Port Buffer VccRTC External RC Circuit VccRTC External RC Circuit ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 1 C3/ S4/S5 COLD Driven Driven Driven Driven Driven Driven Driven ...
Page 93
... ICH6 is in the S3 2. LAN Connect and EEPROM signals will either be “Driven” or “Low” in S3–S5 states depending upon whether or not the LAN power planes are active. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Driver During Reset Vcc3_3 ...
Page 94
... Pin States 94 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 95
... Differential clock pair used for SATA. Generator Main Clock 100 MHz Differential clock pair used for DMI. Generator Free-running PCI Clock to Intel Main Clock remains on during S0 and S1 (in desktop) state, and is 33 MHz Generator expected to be shut off during S3 or below in desktop configurations below in mobile configurations ...
Page 96
... SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair 50 MHz LAN Connect 12.288 MHz AC ’97 Codec(s) 24 MHz ® Intel § ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet PCI Clocks (33 MHz) Clock Gen. 14.31818 MHz 48.000 MHz PCI Express Differential ...
Page 97
... The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the cycle types shown in Table 5-1. PCI Bridge Initiator Cycle Types Command I/O Read/Write Memory Read/Write Configuration Read/Write Special Cycles ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Table 5-1. C/BE# Notes 2h/3h Non-posted 6h/7h ...
Page 98
... FRAME# at the next legal clock edge when there is another active request to use the PCI bus. 5.1.2.7 Dual Address Cycle (DAC) The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB. 98 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 99
... This is a slight deviation from the PCI bridge spec, which says that a cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 99 ...
Page 100
... ICH6 asserts AD17. This mapping continues all the way up to device 15 where the ICH6 asserts AD31. Note that the ICH6’s internal functions (AC ’97, Intel High Definition Audio, IDE, USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. The integrated LAN controller is Device 8 on the ICH6’ ...
Page 101
... One or more bits set to 1, software clears some (but not all) bits One or more bits set to 1, software clears all bits Software clears one or more bits, and one or more bits are set on the same clock ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Interrupt Register Functional Description Wire-Mode Action ...
Page 102
... RCTL.PIE is later written from and interrupt must be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state. 102 . When a device is put into HOT Section 5.2.2.4 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet for SMI/SCI ...
Page 103
... SLSTS.PDS (D28:F0/F1/F2/F3:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3:Offset 58h: bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3:Offset 58h:bit 5) are both set, the root port will also generate an interrupt. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet PCICMD.SEE Correctable SERR# Fatal SERR# ...
Page 104
... If SLCTL.ABE (D28:F0/F1/F2/F3:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/F3:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated. 104 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 105
... Support of Wired for Management (WfM) Revision 2.0 • Backward compatible software with 82550, 82557, 82558 and 82559 • TCP/UDP checksum off load capabilities • Support for Intel’s Adaptive Technology ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description Section 5 ...
Page 106
... Any master access to the LAN controller after the completion of the EEPROM read is honored. 106 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 107
... In the D3 state, the LAN controller can provide wake-up capabilities. Wake-up indications from the COLD LAN controller are provided by the Power Management Event (PME#) signal. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 107 ...
Page 108
... NetBIOS over TCP/IP (NBT) Query Packet (under IPv4) • Internetwork Package Exchange* (IPX) Diagnostic Packet This allows the LAN controller to handle various packet types. In general, the LAN controller supports programmable filtering of any packet in the first 128 bytes. 108 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 109
... EEPROM or eight bits for a 256-register EEPROM. The end of the address field is indicated by a dummy 0 bit from the EEPROM, which indicates the entire address field has been transferred to the device. An EEPROM read instruction waveform is shown in Figure 5-2. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 109 ...
Page 110
... Following reset, the CSMA defaults to automatically track the platform LAN Connect component duplex mode. The selection of duplex operation (full or half) and flow control is done in two levels: MAC and LAN Connect. 110 READ OP code ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 111
... The SMLink is a dedicated bus between the LAN controller and the integrated ASF controller (if enabled external management controller. An EEPROM of 256 words is required to support the heartbeat command. 5.3.5.1 Advanced TCO Mode The Advanced TCO functionalities through the SMLink are listed in ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description Table 5-3. 111 ...
Page 112
... Eventually, the ICH6 increments the receive TCO static counter, clears the TCO request bit, and resumes normal control. 112 TCO Controller Functionality ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Section 8.2), and then ...
Page 113
... The stimulus for causing the ASF controller to send packets can be either internal or external to the ASF controller. External stimuli are link status changes or polling data from SMBus sensor devices; internal events come from, among others, a set of timers or an event caused by software. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 113 ...
Page 114
... PET Compliant Packets - RMCP - Legacy Sensor Polling - ASF Sensor Polling - Remote Control Sensor Support • Advanced Features / Miscellaneous — SMBus 2.0 compliant — Optional reset extension logic (for use with a power-on reset) 114 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 115
... Sensor Configuration driver / application Note: Contact your Intel Field Representative for the Client ASF Software Development Kit (SDK) that includes additional documentation and a copy of the client ASF software drivers. Intel also provides an ASF Console SDK to add ASF support to a management console. ...
Page 116
... Figure 5-3. LPC Interface Diagram ® Intel ICH6 SUS_STAT# 116 Figure PCI Bus PCI PCI CLK RST# LAD[3:0] LFRAME# LDRQ# (optional) LPCPD# (optional) LSMI# GPI (optional) ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 5-3. Note that the ICH6 PCI PCI PME# SERIRQ LPC Device ...
Page 117
... Comment Single: 1 byte only Single: 1 byte only ® 1 byte only. Intel ICH6 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. See Note 1 below. 1 byte only. ICH6 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. See Note 1 below. ...
Page 118
... ICH6 ignores those bits. Bits[1:0] are encoded as listed in Table 5-7. Transfer Size Bit Definition Bits[1:0] 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) Reserved. The Intel 10 master cycle drives this combination, the ICH6 may abort the transfer. 11 32-bit transfer (4 bytes) 118 shows the valid bit encodings. I/O Read ...
Page 119
... Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request 0000 de-assertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel 0101 this encoding. Instead, the ICH6 uses the Long Wait encoding (see next encoding below). ...
Page 120
... PLTRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol. 5.5.1.12 Configuration and Intel LPC I/F Decoders To allow the I/O cycles and memory mapped cycles the LPC interface, the ICH6 includes several decoders ...
Page 121
... DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register ® Figure 5-4. Intel ICH6 DMA Controller Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers ...
Page 122
... Similarly 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. 122 Low priority ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Section 10.2. ...
Page 123
... DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Current Byte/Word Count Register Bytes ...
Page 124
... I/O device does not need to self-arbitrate before sending the message. Figure 5-5. DMA Request Assertion through LDRQ# LCLK LDRQ# 124 Figure Start MSB LSB ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 5-5, the peripheral uses the ACT Start ...
Page 125
... The peripheral indicates data ready through SYNC and transfers the first byte. — 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 125 ...
Page 126
... DMA request will remain active to the 8237 later time, the ICH6 will then come back with another START another transfer to the peripheral. 126 CYCTYPE CHANNEL SIZE etc. combination to initiate – – – ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 127
... To that end recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow with a bus mastering interface and not rely on the 8237. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 127 ...
Page 128
... A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format. 128 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 129
... The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Function Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed ...
Page 130
... The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. 130 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 131
... Therefore, the term “high” indicates “active,” which means “low” originating PIRQ#. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Typical Interrupt Source ...
Page 132
... Table 5-14. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 132 defines the IRR, ISR, and IMR. Description Bits [7:3] Bits [2:0] 111 110 101 100 ICW2[7:3] 011 010 001 000 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 133
... Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set Special mask mode is cleared and Status Read is set to IRR. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 133 ...
Page 134
... ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set indicate that the controllers are operating in an Intel Architecture-based system. 5.9.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. • ...
Page 135
... Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 135 ...
Page 136
... From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. 136 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 137
... Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH6 receives the PIRQ input, like all of the other external sources, and routes it accordingly. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 137 ...
Page 138
... HPET #2, Option for SCI, TCO No Yes No No FERR# logic IDEIRQ (legacy mode, non-combined or combined 1 Yes Yes mapped as primary), SATA Primary (legacy mode) IDEIRQ (legacy mode — combined, mapped as Yes Yes secondary), SATA Secondary (legacy mode) ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Internal Modules ...
Page 139
... The address and data formats are described below in Section 5.10.4.4. Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the ICH6. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Direct from Via PCI Pin Message ...
Page 140
... Destination Mode bit are both set to 1, then the logical destination mode is used, and 2 the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00. 140 Table 5-16 and Table 5-17 for the address and data. Description ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 141
... Serial Interrupt pin. If IRQ14/IRQ15 are shared with the Serial Interrupt pin then abnormal system behavior may occur. For example, IRQ14/IRQ15 may not be detected by the ICH6’s interrupt controller. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description Description ...
Page 142
... IRQ2 15 frames indicates that an active-high ISA interrupt is – – Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame ® Continuous Mode. Only the host (Intel ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ICH6) may initiate a Start Frame ...
Page 143
... IRQ14 16 IRQ15 17 IOCHCK# 18 PCI INTA# 19 PCI INTB# 20 PCI INTC# 21 PCI INTD# ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Clocks Past Start Frame 2 Ignored. IRQ0 can only be generated via the internal 8524 5 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit Ignored ...
Page 144
... To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 144 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 145
... RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced—all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description Table 5-20 ...
Page 146
... TCO1 Status Register TCOBase + 04h (TCO1_STS) TCO2 Status Register TCOBase + 06h (TCO2_STS) Backed Up Control Chipset Configuration Register (BUC) Registers:Offset 3414h Backed Up Control Chipset Configuration Register (BUC) Registers:Offset 3414h ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Default Bit(s) State 7 ...
Page 147
... CPUSLP#, CPUPWRGD • Standard Input from processor: FERR# • Intel SpeedStep Most ICH6 outputs to the processor use standard buffers. The ICH6 has separate V_CPU_IO signals that are pulled up at the system level to the processor voltage, and thus determines V the outputs to the processor. ...
Page 148
... If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. 148 Comment transition on RCIN# must occur before the Intel ICH6 will arm INIT generated again. NOTE: RCIN# signal is expected to be high during S3 and low during S3 ...
Page 149
... Processor Power Good (CPUPWRGOOD) This signal is connected to the processor’s PWRGOOD input. In mobile configurations to allow for Intel SpeedStep technology support, this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH6’s PWROK and VRMPWRGD signals ...
Page 150
... In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by the processors. The Intel ICH6 also has the option to assert the processor’s SLP# signal (CPUSLP#). It is assumed that prior to setting the SLP_EN bit that causes the transition to the S1 state, the processors will not be executing code that is likely to delay the Stop-Grant cycles. In going to the S3, S4 states, the system will appear to pass through the S1 state ...
Page 151
... Table 5-24 shows the power states defined for ICH6-based platforms. The state names generally match the corresponding ACPI states. Table 5-24. General Power States for Systems Using Intel State/ Substates Full On: Processor operating. Individual devices may be shut down to save power. The ...
Page 152
... Functional Description Table 5-25. State Transition Rules for Intel Present State • Processor halt instruction • Level 2 Read • Level 3 Read (Mobile Only) • Level 4 Read (Mobile Only) G0/S0/C0 • SLP_EN bit set • Power Button Override • Mechanical Off/Power Failure • ...
Page 153
... Section 10.1.13). The interrupt remains asserted until all SCI sources are removed. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet By The SLP_S3# signal can be used to cut the power to the processor completely. The DPRSLPVR support allows lowering the processor’s voltage during the C4 state ...
Page 154
... No Yes none No Yes none No Yes NMI2SMI_EN=1 No Yes INTRD_SEL=10 No Yes BLD=1 No Yes BIOSWP=1 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Where Reported PME_STS PME_B0_STS PCI_EXP_STS HOT_PLUG_STS PWRBTN_STS PRBTNOR_STS RTC_STS RI_STS AC97_STS USB1_STS USB2_STS USB3_STS USB4_STS THRM_STS TMROF_STS GPI[x]_STS GPE0_STS TCOSCI_STS ...
Page 155
... BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event UHCI USB Legacy logic Serial IRQ SMI reported Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message ...
Page 156
... C2 C4. The break events from Breaks from IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O C2, C3, C4 APIC. Since SCI is an interrupt, any SCI will also be a break event. C2, C3, C4 Many possible sources ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Comment ...
Page 157
... ICH6 sees no bus master activity. • A break event occurs. In this case, the ICH6 will perform the sequence. Note that bus master traffic is not a break event in this case. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Breaks from Comment Could be indicated by the keyboard controller via the C2, C3, C4 RCIN input signal ...
Page 158
... Cycles on PCI or LPC • Cycles of any internal device that would need the PCI bus • SERIRQ activity 158 Used by PCI and LPC peripherals to request the system PCI clock to run Used to stop the system PCI clock ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 159
... LPC device after the assertion of STP_PCI#. Upon de-assertion of STP_PCI#, the ICH6 assumes that the LPC device receives its first clock rising edge corresponding to the ICH6’s second PCI clock rising edge after the de-assertion. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 159 ...
Page 160
... Wake events that occur while BATLOW# is asserted are latched by the ICH6, and the system wakes after BATLOW# is de-asserted. 160 Comment ICH6 asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This Table ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 5-30. ...
Page 161
... Table 5-30. Causes of Wake Events 1,2 Cause RTC Alarm Power Button GPI[0:15] Classic USB LAN RI# AC ‘97 / Intel High Definition Audio Primary PME# Secondary PME# PCI_EXP_WAKE# PCI_EXP PME Message SMBALERT# SMBus Slave Message SMBus Host Notify message received NOTES the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events are due to Power ...
Page 162
... Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Table 5-32. Transitions Due to Power Failure State at Power Failure S0, S1 162 AFTERG3_EN bit Transition When Power Returns ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet -standby goes high CC ...
Page 163
... If both the THTL_EN and FORCE_THTL bits are set, then the ICH should use the duty cycle defined by the THRM_DTY field, not the THTL_DTY field. 5.14.8.4 Active Cooling Active cooling involves fans. The GPIO signals from the ICH6 can be used to turn on/off a fan. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 163 ...
Page 164
... SCI_EN) Wake Event. Transitions to S0 state None Unconditional transition to S5 state seconds ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 5-33. Note that the transitions start as Comment Software typically initiates a Sleep state Standard wakeup No effect since no power Not latched nor detected No dependence on processor (e ...
Page 165
... S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Event ...
Page 166
... C3 state, the BMBUSY# signal is active, then the BM_STS bit will be set. If after going to the C3 state, the BMBUSY# signal goes back active, the ICH6 will treat this as if one of the PCI REQ# signals went active. This is treated as a break event. 166 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 167
... If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 167 ...
Page 168
... C6h 2 C8h 2 2 CAh 2 CCh 2 CEh 2 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Restore Data Data 1 Timer Counter 0 status, bits [5:0] 2 Timer Counter 0 base count low byte Timer Counter 0 base count high 3 byte 4 Timer Counter 1 base count low byte Timer Counter 1 base count high ...
Page 169
... PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-36. Table 5-36. PIC Reserved Bits Return Values PIC Reserved Bits ICW2(2:0) ICW4(7:5) ICW4(3:2) ICW4(0) OCW2(4:3) OCW3(7) OCW3(5) OCW3(4:3) ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet I Data Access Addr Rds D0h Value Returned 000 ...
Page 170
... FETs to the motherboard. 170 Table 5-37 have write paths to them in ALT access mode. Software Register Write Value DMA Status Register for channels 0–3. DMA Status Register for channels 4–7. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet and HOT ...
Page 171
... ICH6 has no dependency on the order in which these two signals go active or inactive. 5.14.11.6 BATLOW# (Battery Low) (Mobile Only) The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not sufficient power. It also causes an SMI# if the system is already state. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 171 ...
Page 172
... Main Clock Used by ACPI timers. Stopped based on SLP_S3# Generator assertion. AC-link. Control policy is determined by the clock source. AC ’97 Codec NOTE: Becomes clock output when Intel High Definition Audio is enabled. 0.8 to LAN LAN Connect Interface. Control policy is determined by the Connect clock source. ...
Page 173
... Clock Control Signals from Intel Synthesizer (Mobile Only) The clock generator is assumed to have direct connect from the following ICH6 signals: • STP_CPU# • STP_PCI# • SLP_S3# 5.14.13 Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms ...
Page 174
... The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. 174 Section 7.1.56) ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 175
... The event messages are sent based on events occurring. The heartbeat messages are sent every seconds. When an event occurs, the ICH6 sends a new message and increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Section 5.15.2). ...
Page 176
... If the intervention occurs before the third timeout, then jump to rule/step 11. 4. After step 3 (third timeout), if the user does a Power Button Override, the system goes state. The ICH6 continues sending heartbeats at this point. 176 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 177
... ICH6 waits until the bus is idle, and tries again. 2. WARNING important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the LAN device driver from working properly. The alerts reset part of the LAN controller ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 177 ...
Page 178
... Comment 1 = This bit is set if the intruder detect bit is set (INTRD_DET). ® This bit is set if the Intel ICH6 THERM# input signal is asserted This bit is set if the processor failed to fetch its first instruction This bit is set when the TCO timer expires This bit is set when software writes the SEND_NOW bit. ...
Page 179
... The command strobe assertion width for the enhanced timing mode is selected by the IDE_TIM Register and may be set PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set PCI clocks. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 179 ...
Page 180
... IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. Only 16-bit buffer writes are supported. 180 Table 5-40. Startup IORDY Sample Recovery Time Latency Point (ISP) (RCT 2–5 1–4 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Shutdown Latency ...
Page 181
... Figure 5-7. Physical Region Descriptor Table Entry Byte 3 Memory Region Physical Base Address [31:1] EOT Reserved ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Byte 2 Byte 1 Byte 0 Byte Count [15:1] Functional Description Main Memory ...
Page 182
... At the end of the transfer, the IDE device signals an interrupt response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the controller status followed by the drive status to determine if the transfer completed successfully. 182 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 183
... Count) can be used to determine how much of the transfer was completed and to construct a new PRD table to complete the requested operation. In most cases the existing PRD table can be used to complete the operation. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet describes how to interpret the Interrupt and Active bits in the Status Register Description DMA transfer is in progress ...
Page 184
... DMACK#. The ICH6 terminates a burst transfer if it needs to service the opposite IDE channel Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the final PRD. 184 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet writes, IDE – ...
Page 185
... SMI# is generated, and the device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating that a trap occurred. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description Section 11 ...
Page 186
... EDD command and asserts INTR. Software must wait for BSY to clear before completing an EDD command, as required by the ATA5 through ATA7 (T13) industry specifications. 186 Section 12.1.29, provides the ability to share PCI functions. When sharing is ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 187
... Intel Application Accelerator RAID Option ROM The Intel Application Accelerator RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions: ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 188
... Slumber – PHY logic is powered, but in a reduced state. Exit latency can ms. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller defines these states as sub-states of the device D0 state. 188 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 189
... When the power state is D3, no interrupts may be generated, even if they are enabled interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Power ® Intel ICH6 SATA Controller = D0 Device = D0 Device = D1 PHY = PHY = PHY = PHY = ...
Page 190
... See section 7.3.1 of the AHCI Specification for more information. 190 Section 12.1.40) contain control for generating SMI# on – (Section 12.1.41) are updated indicating that a trap ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet 1F7h, 3F6h, 170 177h, – ...
Page 191
... Per IRQ Routing Field. Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF Each timer has its own routing control. The supported interrupt values are IRQ 20, 21, 22, and 23. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet APIC Mapping IRQ0 IRQ2 ...
Page 192
... The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 04h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable 4. Set the comparator value 192 20.1.5). ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 193
... If a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper 32-bits are always 0. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description Section 5.10 ...
Page 194
... The last two bits in the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in the packet must be indexed from this point. 194 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 195
... USB function #3, PIRQD# pin for USB function #1, and the PIRQC# pin for USB function #2, until all sources of the interrupt are cleared. In order to accommodate some operating systems, the Interrupt Pin register must contain a different value for each function of this new multi-function device. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 195 ...
Page 196
... This feature streamlines the processing of input on these transfer types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. 196 ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet ...
Page 197
... C_ERR field decrements to 0, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is set the end of the frame and a hardware interrupt is signaled to the system. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Functional Description 197 ...
Page 198
... ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI generated. 198 Offset Bit 00h 3 Enter Global Suspend Mode (EGSM) 02h 2 Resume Detect 2 Port Enabled/Disabled 6 Resume Detect 10h & 12h 8 Low-speed Device Attached 12 Suspend ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Description ...
Page 199
... An additional term is required for the “pass-through” case. The state table for Figure 5-9 Figure 5-9. USB Legacy Keyboard Flow Diagram KBC Accesses PCI Config Read, Write USB_IRQ Clear USB_IRQ ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet is shown in Table 5-44. 60 READ S D Clear SMI_60_R Comb. ...
Page 200
... Bit 7 in Configuration Register is set, then SMI# should be generated. Improper end of sequence. Bit 0 in Configuration Register determines if cycle passed through to N/A IDLE 8042 and if SMI# generated. PSTATE goes Bit 7 in Configuration Register is set, then SMI# should be generated. ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet Comment ...