NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet
NH82801HBM S LA5Q
Specifications of NH82801HBM S LA5Q
Related parts for NH82801HBM S LA5Q
NH82801HBM S LA5Q Summary of contents
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... Intel I/O Controller Hub 8 (ICH8) Family Specification Update ® – For the Intel 82801HB ICH8, 82801HR ICH8R, 82801HH ICH8DH, and 82801HO ICH8DO, 82801HBM ICH8M, and 82801HEM ICH8M-E I/O Controller Hubs June 2010 ® Notice: The Intel ICH8 may contain design defects or errors known as errata which may cause the product to deviate from published specifications ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Core, Intel Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. ...
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... Contents Contents Revision History ........................................................................................................ 4 Preface ...................................................................................................................... 7 Summary Table of Changes ....................................................................................... 8 Identification Information ....................................................................................... 11 Errata ...................................................................................................................... 13 Specification Changes.............................................................................................. 21 Specification Clarifications ...................................................................................... 23 Document Changes .................................................................................................. 24 ® Intel ICH8 Family Specification Update 3 ...
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... Added 82801HH ICH8DH and 82801HO ICH8DO. • Added Items: ® -003 • Errata: 5-Intel ICH8 PCI Express* Root Port Power State Value, 6-Intel APM Wakeup After G3 • Added Items: ® • Errata: 7-Intel ICH8 Integrated LAN DMA Error, 8-Intel ...
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... Document Change: 10-Add ballout AH19(VSS) to Table 147 • Added: — Errata: 25-Intel® I/O Controller Hub 8 (ICH8) Family PCI Express Function Disable -019 — Document Change: 11-Correct Section 5.13.7.5 Sx-G3-Sx, Handling Power Failures regarding possible wake events following a power failure • ...
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... Intel ICH8 Family Specification Update § § 6 ...
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... These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. ® Intel ICH8 Family Specification Update Title Document Number 313056-003 ...
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... ® Intel ICH8 Family Specification Update ® I/O Controller Hub 8 (ICH8) family. Intel intends to Status No fix Intel ICH8 TCO Mode Strap No Fix Intel ICH8 1.5-Gb/s SATA Signal Voltage Level Intel ICH8 Reset Command Received through SMBus during No Fix Suspend Intel ICH8 Forced Shutdown Event with Integrated GbE LAN ...
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... No Fix ICH8 Thermal Sensor Temperature Reading No Fix Intel(R) ICH8/ICH8M USB Resume EOP missing No Fix Intel(R) ICH8M IDE input buffer V+ & Vih spec violation ICH8 High Speed (HS) USB 2.0 D+ and D- maximum Driven Signal No Fix Level No Fix ICH8 GbE Packet Buffer Writing Error ...
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... Add ballout AH19(Vss) to Table 147 Correct Section 5.13.7.5 Sx-G3-Sx, Handling Power Failures regarding possible wake events following a power 11 failure 12 Correct section 9.1.21 Bits 15:2 definition 13 Correct Figure 20 and Figure 21 Ballout information 14 Correct section 11.1.43 bit 0 definition ® Intel ICH8 Family Specification Update DOCUMENTATION CHANGES 10 ...
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... SL9MN B0 SL9MK B0 SL9ML BO SL9MM B1 SLA5Q B1 SLA5R B2 SLB9A B2 SLB9B ® Intel ICH8 Family Specification Update Top Marking NH82801HB 82801HB ICH8 Base NH82801HR 82801HR ICH8R NH82801HH 82801HH ICH8DH NH82801HO 82801HO ICH8DO NH82801HBM 82801HBM ICH8M Base NH82801HEM 82801HME ICH8M-E Enhanced NH82801HBM 82801HBM ICH8M Base ...
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... BIOS and what RAID capabilities exist in the ICH8 component. 2. Loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the device ID location, then 104Bh is used. Refer to the ICH8 EEPROM Map and Programming Guide for LAN Device IDs. ® Intel ICH8 Family Specification Update ICH8 ICH8 ICH8 ® ...
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... TX connector and device RX connector voltage specifications (section 7.2.1 of Serial ATA Specification, rev 2.5). Implication: None known. Workaround:None. Status: No plan to fix. For affected steppings, see the Summary Table of Changes. ® Intel ICH8 Family Specification Update 13 ...
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... SMBus wake command will not cause the system to wake. ® Note: Intel Active Management Technology is not impacted as Intel Reset Without Cycling command while the system is in S3. Note: Any SMBus read that is accepted by the ICH8 will complete normally. Workaround:Do not send a Hard Reset Without Cycling command while the system is in S3. ...
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... NVM Change: Program bit 1 of Word 0x13h the ICH8 GbE NVM image. This is implemented in NVM version 1.1 and later. • Through extensive validation and focused testing, Intel has not observed failures with bit 1 of Word 0x13h set the ICH8 NVM image. To protect against a theoretical case where the issue could occur even when the NVM image is updated, Intel recommends a driver update that customers should implement as soon as feasible ...
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... Implication: There is no known impact to platform functionality. The platform may flag a failure for each bit field with Microsoft Vista* Compliance test. Workaround:None. Intel is working with Microsoft to get contingencies for the failures. Status: No Fix. For steppings affected, see the Summary Tables of Changes. ...
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... EOP as required by the USB 2.0 specification. Implication: A USB LS/FS device that wakes the system may stop functioning after the system resumes from S3-S4. There is no known impact to USB HS devices. Workaround:BIOS workaround available; Contact your Intel field representative for the latest BIOS information Status: No Fix ...
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... The receiver is pseudo differential design • The receiver is not able to ignore SE1 (single-ended) state Note: Intel has only observed this issue with a motherboard down HS USB 2.0 device using pseudo differential design. This issue will not affect HS USB 2.0 devices with complementary differential design or Low Speed (LS) and Full Speed (FS) devices Workaround:None ...
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... SMBus slave receives back-to-back PET alerts of which some PET alerts are incomplete (i.e. the packet is truncated to less than 6 bytes) Note: This issue has only been observed under a synthetic test environment. ® Implication: Intel ME firmware may stop functioning, which could cause a system hang. Workaround:None Status: No Fix ...
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... The ICH8M B2 Stepping Gigabit Ethernet Controller (B0:D25:F0) may report an incorrect Revision-ID when Compatibly Revision-ID is enabled. Implication: The OS image may re-enumerate the Intel ICH8M B2 Gigabit Ethernet Controller when Compatibly Revision-ID is enabled. • LAN devices affected are Intel - This may impact customer platforms that are part of Intel SIPP) ...
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... This feature allows platforms (especially mobile systems) to dynamically enter low-power states during brief periods when the system is idle (i.e., between keystrokes). This is useful for enabling power management features like Intel SpeedStep these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do ...
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... Removing Support for USB Wake from S5 Support for USB wake from S5 is removed from the Datasheet as indicated below. ® a. Update Intel ICH8 Features page of the Datasheet as follows: USB 2.0 —NEW five UHCI Host Controllers, supporting ten external ports —NEW two EHCI Host Controllers that support ten external ports — ...
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... Note 23 in Table 173 of the Datasheet is changed as indicated below: 23. t294 applies during S0 to S3/S4/S5 and transitions. V5REF timings are bounded by power sequencing. b. Figure 52 and Figure 53 of the Datasheet is modified to ® Intel ICH8 Family Specification Update These three bits control the divider chain for the . 6 ...
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... SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the interface and host. The ICH8 updates it continuously and asynchronously. When the ICH8 transmits a COMRESET to the device, this register is updated to its reset values. Bit 31:12 Reserved ® Intel ICH8 Family Specification Update Attribute: RO Size: 32 bits Description ...
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... Reserved 19:16 Port Multiplier Port (PMP) — RO. This field is not used by AHCI. 15:12 Select Power Management (SPM) — RO. This field is not used by AHCI. ® Intel ICH8 Family Specification Update Description Description Device not present or communication not established Interface in active state Interface in PARTIAL power management state ...
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... If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 31:27 Reserved ® Intel ICH8 Family Specification Update Description Description No interface restrictions Transitions to the PARTIAL state disabled ...
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... PhyNRdy signal between the Phy and Link layers. Recovered Data Integrity Error (I): A data integrity error occurred that was 0 recovered by the interface through a retry operation or other recovery action. ® Intel ICH8 Family Specification Update Description 27 ...
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... This register corresponds to GPIO[31:0]. 10. Add Ballout AH19(VSS) to Table 147 The following is added to Table 147: Ballout by Signal Name (Mobile Only) of the Datasheet Ball Name Ball# VSS AH19 ® Intel ICH8 Family Specification Update 125 MHz domain. Description Each bit in this register corresponds to one of the 28 ...
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... Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. 12. Correct section 9.1.21 Bits 15:2 definition Correct section 9.1.21 GEN1_DEC-LPC I/F Generic Decode Range 1 Register in the Datasheet ® Intel ICH8 Family Specification Update -standby goes high before RSMRST# goes high ...
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... Correct section 11.1.43 bit 0 definition Correct section 11.1.43 CIR5 - Chipset Initialization Register 5 in the EDS and Datasheet 11.1.43 CIR5—Chipset Initialization Register 5 Offset Address: 1D40h–1D47h Default Value: 0000000000000000h ® Intel ICH8 Family Specification Update Attribute: R/W Size: 32 bit Power Well: Core Description ...
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... Bit 63:10 Reserved 0 CIR5 Field 1 - R/W. BIOS must program this field to 1b. ® Intel ICH8 Family Specification Update Description § § 31 ...