ISP1760ETGA STEricsson, ISP1760ETGA Datasheet
ISP1760ETGA
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ISP1760 Hi-Speed USB host controller for embedded applications Rev. 08 — 13 April 2010 1. General description The ISP1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic processor interface. It integrates one Enhanced Host Controller Interface ...
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Slave DMA support to reduce the load of the host system CPU during the data transfer to or from the memory Integrated Phase-Locked Loop (PLL) with a 12 MHz crystal or an external clock input Integrated multi-configuration FIFO Optimized ‘msec-based’ ...
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... LQFP128; 128 leads; body 14 × 20 × 1.4 (mm) single tray dry pack ISP1760BEGA TFBGA128; 128 balls; body 9 × 9 × 0.8 (mm) ISP1760ETUM TFBGA128; 128 balls; body 9 × 9 × 0.8 (mm) ISP1760ETGA CD00222702 Product data sheet Embedded Hi-Speed USB host controller Packing 13-inch tape and reel dry pack single tray dry pack Rev. 08 — ...
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Block diagram 47, 49, 51, 52 74, RISC PROCESSOR 76 to 78, 80 DATA[15:0]/DATA[31:0] 82, 84, ...
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... Pin configuration (LQFP128); top view Fig 3. Pin configuration (TFBGA128); top view CD00222702 Product data sheet Embedded Hi-Speed USB host controller 1 102 ISP1760BEUM ISP1760BEGA 38 65 004aaa505 ball A1 index area ISP1760ETUM J ISP1760ETGA Rev. 08 — 13 April 2010 ISP1760 004aaa550 © ST-ERICSSON 2010. All rights reserved 105 ...
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Pin description Table 2. Pin description [1][2] Symbol Pin LQFP128 TFBGA128 OC3_N 1 C2 REF5V 2 A2 TEST1 3 B2 GNDA 4 A1 REG1V8 CC(5V0 CC(5V0) GND(OSC REG3V3 9 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 PSW2_N 28 M1 GND(RREF3 RREF3 30 N1 [6] GNDA 31 P2 DM3 32 P1 GNDA 33 R2 DP3 34 R1 PSW3_N 35 T1 GNDD 36 T2 DATA0 37 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA9 49 T8 REG1V8 50 R8 DATA10 51 P9 DATA11 52 T9 GNDC 53 R9 DATA12 54 T10 GNDD 55 R10 DATA13 56 P11 DATA14 57 T11 DATA15 58 R11 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA21 66 R15 V 67 P15 CC(I/O) DATA22 68 T16 DATA23 69 R16 DATA24 70 P16 GNDD 71 N16 DATA25 72 N15 DATA26 73 M15 DATA27 74 M16 V 75 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 A2 84 H15 REG1V8 85 G16 A3 86 H14 A4 87 F16 GNDC 88 G15 A5 89 F15 GNDD 90 E16 A6 91 F14 A7 92 E15 A8 93 D16 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 CS_N 106 A12 RD_N 107 B12 WR_N 108 B11 GNDD 109 A11 BAT_ON_N 110 C10 n.c. 111 A10 IRQ 112 B10 n.c. 113 A9 DREQ 114 B9 V 115 C8 ...
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Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 TEST7 126 A4 OC1_N 127 B3 OC2_N 128 A3 [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. [2] All ground pins should normally be ...
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Functional description 7.1 ISP1760 internal architecture: advanced ST-Ericsson slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced ST-Ericsson slave host controller. The EHCI is the latest generation ...
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Fig 4. Internal hub 7.1.1 Internal clock scheme and port selection The ISP1760 has three ports. Fig 5. ISP1760 clock scheme Figure 5 shows that the host clock is derived from port 2. Port 2 does not need to be ...
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Table 3. Port connection scenarios Port configuration Port 1 One port (port 1) DP and DM are routed to USB connector One port (port 2) DP and DM are not connected (left open) One port (port 3) DP and DM ...
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A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB ...
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The address range of the internal RAM buffer is from 0400h to FFFFh. • The internal memory contains isochronous, interrupt and asynchronous PTDs, and respective defined payloads. • All accesses to the internal memory are double word aligned. • ...
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Both the CPU interface logic and the USB host controller require access to the internal ISP1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing ...
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Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch data. That is, the fetching of data is independent of the address on A[15:0] lines. – Write ...
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The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1760 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, ...
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Enable ENABLE_DMA (bit 1) of the DMA Configuration register to determine the assertion of DREQ immediately after setting the bit. After programming the preceding parameters, the system’s DMA may be enabled, waiting for the DREQ to start the transfer ...
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If an event of interrupt occurs but the respective bit in the Interrupt Enable register is not set, then the respective Interrupt register bit is set but the interrupt signal is not asserted. An interrupt will be generated when ...
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Table 5. PTD AND register 7.5 Phase-Locked Loop (PLL) clock multiplier The internal PLL requires a 12 MHz input, which can be ...
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The SUSPEND/WAKEUP_N pin is a 3-state output also an input to the internal wake-up logic. When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of the SUSPEND/WAKEUP_N pin: • remains pulled-up, no ...
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Overcurrent detection The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit is integrated ...
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USB device. Because of this internal delay, as soon as OCn_N is asserted, PSWn_N will switch off the external PMOS in less than 15 ms. 7.8 Power supply Figure 8 shows ...
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Hybrid mode Table 6 shows the description of hybrid mode. Table 6. Voltage V CC(5V0) V CC(I/O) In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current, ...
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To give a better view of the functionality, dips and t4 to t5. If the dip too short, that is, < 11 μs, the internal POR pulse will not react and ...
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Registers Table 8 shows the bit description of the registers. • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. In the case of a 16-bit data ...
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Table 8. Address 0018h 0340h 0344h 0354h 0374h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. CAPLENGTH ...
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Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol N_CC[3:0] Reset 0 0 Access R R Bit 7 6 Symbol PRR Reset 0 0 Access R R Table 12. Bit ...
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Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol Reset 1 0 Access R R Table 14. Bit ...
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Table 15. USBCMD - USB Command register (address 0020h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W ...
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Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol reserved Reset 0 0 Access R/W R/W [1] The reserved bits should always be written with ...
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Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 [1] Symbol reserved Reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Access R/W R/W [1] The reserved bits should always be written ...
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Table 22. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2.6 PORTSC1 register The Port Status and Control (PORTSC) register (bit allocation: well reset by hardware only when ...
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Table 24. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. ...
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Table 26. ISO PTD Skip Map register (address 0134h) bit description Bit Symbol Access ISO_PTD_SKIP_ R/W MAP[31:0] When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its ...
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INT PTD Last PTD register The bit description of the register is given in Table 30. INT PTD Last PTD register (address 0148h) bit description Bit Symbol Access Value INT_PTD_LAST R/W _PTD[31:0] Once the LastPTD bit ...
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Table 33. ATL PTD Last PTD register (address 0158h) bit description Bit Symbol Access Value ATL_PTD_LAST R/W _PTD[31:0] Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V ...
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Table 35. Bit 8.3.2 Chip ID register Read this register to get the ID of the ISP1760. The upper word of the ...
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Scratch register This register is for testing and debugging purposes only. The value read back must be the same as the value that was written. The bit description of this register is given in Table 37. Scratch register (address ...
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Table 40. DMA Configuration register (address 0330h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit ...
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Buffer Status register The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is, ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets the Buffer Filled ...
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Table 43. Bit Symbol 0 ATL_BUF_ FILL 8.3.7 ATL Done Timeout register The bit description of the ATL Done Timeout register is given in Table 44. ATL Done Timeout register (address 0338h) bit description Bit Symbol Access ...
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Table 46. Bit 8.3.9 Force Hub Configuration register The bit description of the register is given in Table 47. Force Hub Configuration register (address 0014h) bit allocation Bit 31 30 Symbol ...
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The bit description of the register is given in Table 49. Force Port Enable register (address 0018h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R R Bit 23 22 Symbol Reset 0 0 Access R R Bit ...
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Table 51. Edge Interrupt Count register (address 0340h) bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W ...
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Bit 15 14 Symbol Reset 0 0 Access W W Bit 7 6 Symbol Reset 0 0 Access W W [1] The reserved bits should always be written with the reset value. Table 54. Bit ...
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Table 56. [1] Bit Symbol CLK_OFF_ COUNTER [15: PORT3_PD Port 3 Pull-Down: Controls port 3 pull-down resistors. 11 PORT2_PD Port 2 Pull-Down: Controls port 2 pull-down resistors. 10 VBATDET_ PWR 9 to ...
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Table 56. [1] Bit Symbol 2 OC2_PWR 1 OC1_PWR 0 HC_CLK_ EN For a 32-bit operation, the default wake-up counter value is 10 μs. For a 16-bit operation, the wake-up [1] counter value is 50 ms. In the 16-bit operation, ...
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Table 58. [1] Bit Symbol PORT1_INIT2 PORT1_INIT1 PORT1_POWER [1: [1] For correct port 1 initialization, write 0080 0018h to ...
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Table 60. Bit Symbol ISO_IRQ 8 ATL_IRQ 7 INT_IRQ 6 CLK READY 5 HC_ SUSP DMAEOT INT CD00222702 Product data sheet Interrupt register (address 0310h) bit description Description reserved; write reset value ...
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Table 60. Bit Symbol SOFITL INT 0 - 8.4.2 Interrupt Enable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 61. Interrupt Enable register (address 0314h) bit ...
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Table 62. Bit 8.4.3 ISO IRQ Mask OR register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware ...
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Table 63. ISO IRQ Mask OR register (address 0318h) bit description Bit Symbol Access ISO_IRQ_MASK R/W _OR[31:0] 8.4.4 INT IRQ Mask OR register Each bit of this register (see and is a hardware IRQ mask for each ...
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Table 67. INT IRQ Mask AND register (address 0328h) bit description Bit Symbol Access INT_IRQ_MASK R/W _AND[31:0] 8.4.8 ATL IRQ Mask AND register Each bit of this register corresponds to one of the 32 ATL PTDs defined, ...
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Multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by endpoint data structures, until it reaches the end of the endpoint list. There are three endpoint lists: one for ISO endpoints, ...
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High-speed bulk IN and OUT Table 69 shows the bit allocation of the high-speed bulk IN and OUT, bulk Transfer Descriptor. Table 69. High-speed bulk IN and OUT: bit allocation Bit ...
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Table 70. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - DW3 ...
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Table 70. High-speed bulk IN and OUT: bit description Bit Symbol Access reserved - NrBytes HW — writes Transferred SW — writes [14:0] 0000 DW2 reserved - RL[3:0] ...
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Table 70. High-speed bulk IN and OUT: bit description Bit Symbol Access MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — ...
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High-speed isochronous IN and OUT Table 71 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD). Table 71. High-speed isochronous IN and OUT: bit allocation ...
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Table 72. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ISOIN_5[3:0] HW ...
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Table 72. High-speed isochronous IN and OUT: bit description Bit Symbol Access — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - ...
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Table 72. High-speed isochronous IN and OUT: bit description Bit Symbol Access NrBytesTo SW — writes Transfer[14: reserved - — resets SW — sets CD00222702 Product data sheet Embedded Hi-Speed USB ...
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High-speed interrupt IN and OUT Table 73 shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD). Table 73. High-speed interrupt IN and OUT: bit allocation ...
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Table 74. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 INT_IN_5[3:0] HW ...
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Table 74. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — writes 56 ...
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Table 74. High-speed interrupt IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - ...
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Start and complete split for bulk Table 76 shows the bit allocation of Start Split (SS) and Complete Split (CS) for bulk, asynchronous Start Split and Complete Split (SS/CS) Transfer Descriptor ...
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Table 77. Start and complete split for bulk: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - DW3 63 A ...
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Table 77. Start and complete split for bulk: bit description Bit Symbol Access RL[3:0] SW — writes 24 reserved - DataStartAddress SW — writes [15: reserved - DW1 ...
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Table 77. Start and complete split for bulk: bit description Bit Symbol Access NrBytesToTransfer SW — writes [14: reserved - — sets HW — resets Table 78. Bulk I/O I/O CD00222702 ...
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Start and complete split for isochronous Table 79 shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD). Table 79. Start and complete split for ...
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Table 80. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] HW — ...
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Table 80. Start and complete split for isochronous: bit description Bit Symbol Access — sets HW — resets — writes — writes — writes — ...
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Table 80. Start and complete split for isochronous: bit description Bit Symbol Access reserved - TT_MPS_Len SW — writes [10: NrBytesTo SW — writes Transfer[14: reserved - 0 ...
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Start and complete split for interrupt Table 81 shows the bit allocation of start and complete split for interrupt. Table 81. Start and complete split for interrupt: bit allocation Bit 63 ...
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Table 82. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — ...
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Table 82. Start and complete split for interrupt: bit description Bit Symbol Access μSA[7: — writes (0 → — writes (1 → 0) After processing DW3 — sets HW — resets ...
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Table 82. Start and complete split for interrupt: bit description Bit Symbol Access — writes EPType[1:0] SW — writes Token[1:0] SW — writes DeviceAddress SW — writes [6:0] ...
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Power consumption Table 85. Number of ports working One port working (high-speed Two ports working ...
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Limiting values Table 86. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage (5.0 V) CC(5V0) I latch-up current lu V electrostatic discharge voltage esd T ...
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Static characteristics Table 88. Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; T Symbol Parameter V = ...
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Table 90. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) − 1. 3 CC(I/O) amb Symbol Parameter V high-speed data signaling HSOH HIGH-level voltage V high-speed data ...
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Dynamic characteristics Table 92. Dynamic characteristics: system clock timing − 1. 3 CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input t external clock jitter J δ ...
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Table 95. Dynamic characteristics: full-speed source electrical characteristics − 1. 3 CC(I/O) amb Symbol Parameter Driver characteristics t rise time FR t fall time FF t differential rise and fall time FRFM ...
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PIO timing 14.1.1 Register or memory write Fig 14. Register or memory write Table 97. − amb Symbol 1.95 V CC(I/O) t h11 t h21 t h31 t w11 t su11 ...
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Register read Fig 15. Register read Table 98. − amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t d22 3.6 V ...
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Table 99. − amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 14.1.4 Memory read A[17:1] DATA CS_N WR_N RD_N Fig 17. Memory read Table 100. ...
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Table 100. Memory read − amb Symbol t d23 t w13 t su13 t su23 14.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH. 14.2.1 ...
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Table 101. DMA read (single cycle) − amb Symbol t w14 t a34 t a44 t h14 14.2.2 Single cycle: DMA write DREQ DACK WR_N DREQ and DACK are active HIGH. Fig 19. DMA write (single cycle) ...
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Multi-cycle: DMA read DREQ and DACK are active HIGH. Fig 20. DMA read (multi-cycle burst) Table 103. DMA read (multi-cycle burst) − amb Symbol Parameter 1.95 V CC(I/O) t DACK assertion ...
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Multi-cycle: DMA write Fig 21. DMA write (multi-cycle burst) Table 104. DMA write (multi-cycle burst) − amb Symbol Parameter 1.95 V CC(I/O) T DMA write cycle time cy17 t data set-up ...
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Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 DIMENSIONS (mm are the original dimensions) A UNIT A A ...
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TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 0.8 mm ball A1 index area ball A1 ...
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Abbreviations Table 105. Abbreviations Acronym ACK ASIC ATL ATX CS DMA DW EHCI EMI EOP EOS EOT ESD ESR FIFO FLS FS GPIO HC HNP HS iTD INT ISO ISR ITL LS NAK NYET OC OHCI PCI PDA PID ...
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Table 105. Abbreviations Acronym PTD RISC SE0 SE1 siTD SOF SRP SS TT UHCI USB 17. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 [3] Embedded Systems Design ...
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Revision history Table 106. Revision history Revision Release date 8 20100413 Modifications: Globally removed reference to NextPTDPointer. 7 20091130 6 20090812 5 20090122 4 20080204 3 20070302 2 (9397 750 15189) 20051025 1 (9397 750 13257) 20041108 CD00222702 Product ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . ...
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Table 50. Force Port Enable register (address 0018h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 51. ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration (LQFP128); top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 08 — 13 April 2010 ISP1760 Embedded Hi-Speed USB host controller © ...