N82802AC8 Intel, N82802AC8 Datasheet

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N82802AC8

Manufacturer Part Number
N82802AC8
Description
Manufacturer
Intel
Datasheet

Specifications of N82802AC8

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R
®
Intel
82802AB/82802AC
Firmware Hub (FWH)
Datasheet
November 2000
Document Number:
290658-004

Related parts for N82802AC8

N82802AC8 Summary of contents

Page 1

... R ® Intel 82802AB/82802AC Firmware Hub (FWH) Datasheet November 2000 Document Number: 290658-004 ...

Page 2

... Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...

Page 3

... CUI Automation Flowcharts........................................................................................... 31 5. Electrical Specifications ............................................................................................................. 33 5.1. Absolute Maximum Ratings........................................................................................... 33 Datasheet Intel Firmware Hub Interface....................................................................... 10 Address/Address-Multiplexed Interface ...................................................... T_BLOCK_LK and T_MINUSxx_LK — Block-Locking Registers ............... 25 General-Purpose Input Register ................................................................. 26 GPI_REG — General-Purpose Input Register ............................... 26 Random Number Generator Registers ....................................................... 27 RNG Hardware Status Register ..................................................... 27 RNG Data Status Register ...

Page 4

... Electrical Characteristics in A/A Mux Mode ...................................................................48 6.4.1. 6.4.2. 6.4.3. 6.4.4. 4 Interface DC Input/Output Specifications ....................................................34 Interface AC Input/Output Specifications.....................................................36 Intel FWH Interface AC Timing Specifications ............................................37 Clock Specification..........................................................................37 Signal Timing Parameters...............................................................38 Intel FWH Interface Cycles..........................................................................40 Read Cycle Sequence.....................................................................40 Single-Byte Read Waveforms.........................................................42 Write Cycle Sequence.....................................................................42 Write Waveforms ............................................................................43 Response To Invalid Fields.............................................................43 Abort Operations ...

Page 5

... R Figures Figure 1. Simplified Block Diagram ..................................................................................... 8 Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture .................... 11 Figure 3. Intel FWH Boot-Configuration System Memory Map......................................... 11 Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout......................................................... 13 Figure 5. 40-Lead TSOP Intel Firmware Hub Pinout ........................................................ 13 Figure 6. Automated Block Erase Flowchart..................................................................... 31 Figure 7 ...

Page 6

... Intel 82802AB/AC Firmware Hub Revision History Rev. -001 • Initial Release • Added Chapter 6 -002 • Updated programmer vendor/service provider information. • Changed V -003 • Updated programmer vendor/service provider information. • Clarification of part numbering. • Spec now includes all known issues from all densities/lithographies. ...

Page 7

... Mbits of flash memory for platform code/data nonvolatile storage  Symmetrically blocked, 64-KB memory sections ®  Available in 8-Mbit (Intel 82802AC) and 4- ® Mbit (Intel 82802AB) densities  Automated byte program and block erase via an integrated Write State Machine (WSM) § ...

Page 8

... Intel 82802AB/AC Firmware Hub Figure 1. Simplified Block Diagram SMBus Device(s) AC’97 Codec(s) (optional) IDE (4 drives) 8 Processor Memory Controller SMBus I/O AC’97 Controller IDE USB GPIO Memory ISA Bridge (optional) PCI Bus PCI Slot PCI Agent LPC Interface Super I/O 82802 ...

Page 9

... Resetting the component will put the component back into read-array mode. Note: There is no chip enable (like CE#) in either interface. Stand-by current control in the Inel FWH interface is enabled automatically, if the Intel FWH4 is high and the device is not working to complete a requested activity. Datasheet ® ...

Page 10

... The buffers for this interface were designed to be PCI compliant. To ensure the effective delivery of security and manageability features, the Intel FWH interface is the only way access the full feature set of the device. The Intel FWH interface is equipped to operate at 33 MHz, synchronous with the PCI bus. ...

Page 11

... R Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 Figure 3 ...

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... Intel 82802AB/AC Firmware Hub 12 This page is intentionally left blank. R Datasheet ...

Page 13

... R 2. Pinout Configurations Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout A/A Mux DQ0 A/A Mux Figure 5. 40-Lead TSOP Intel Firmware Hub Pinout A/A Mux FGPI4 A10 NC NC CLK R/C# VCC VCC VPP VPP RST# RST FGPI3 A9 FGPI2 A8 FGPI1 A7 FGPI0 A6 WP# A5 TBL# ...

Page 14

... The pin descriptions table details the usage of each device pin. Most pins have dual functionality, with functions in both the Intel Firmware Hub and A/A Mux interfaces. The A/A Mux functionality for pins is shown bold italic in the description box for that pin. All pins are designed to be compliant with VCC + 0 ...

Page 15

... These pins are pulled down with internal resistors, with 0010,0011,... values between 20 and 100 kΩ, when in the Intel FWH mode. Any ID pins pulled high will exhibit a leakage current of approximately 200 µA. Any pins intended to be low may be left to float single Intel FWH system, all may be left floating ...

Page 16

... CCa GND PWR a RFU NC Ry/By Interface Intel A/A Mux FWH Block Erase/Program Power Supply. For erasing array blocks or programming data. V memory contents cannot be altered. Attempting a block erase program with an invalid V spurious results and should not be attempted for 80 hours over the lifetime of the device. ...

Page 17

... Output Disable When the Intel FWH is not selected through a FWH read or write cycle, the Intel FWH interface outputs (FWH[3:0]) are disabled and is placed in a high-impedance state. 3.4. ...

Page 18

... Operational Effects of Hardware Write-Protect Pins TBL# and WP# The TBL# and WP# pins on the Intel FWH provide hardware write protect capabilities. The Top Block Lock (TBL#) pin, when held low (active), prevents program or block erase operations in the top-most block of the device where critical code can be stored. When TBL# is high, hardware write protection of the top block is disabled ...

Page 19

... Either 40h or 10h are recognized by the WSM as the program setup. Note: Commands other than those shown previously are reserved by Intel for future device implementations and should not be used. Datasheet , read operations from the status register, identifier codes or memory are ...

Page 20

... Intel 82802AB/AC Firmware Hub Table 3. Status Register Definition 7 WSMS Bit 7 Write State Machine Status (SR.7). Check SR.7 to determine block erase or program completion. SR.6–0 are invalid while SR Ready 0 = Busy 6 Erase Suspend Status (SR.6 Block erase suspended 0 = Block erase in progress/completed 5 Erase Status (SR.5). If both SR.5 and SR.4 are 1s after a block erase attempt, an improper command sequence was entered ...

Page 21

... ID data from the addresses shown in the following table. To terminate the read identifier code operation, write another valid command to the Intel FWH. The Read Identifier Codes command functions independently of the V voltage ...

Page 22

... Intel 82802AB/AC Firmware Hub 4.5. Block Erase Command The erase command operates on one block at a time. This command requires an (arbitrary) address within the block to be erased. Recall that erasure changes all block data to FFh. Block preconditioning, erase, and erase verify are handled internally by the WSM, which is transparent to the system. After issuing the erase command, the device automatically outputs status register data when read ...

Page 23

... Register Based Locking, General-Purpose Input, and Random Number Generator Registers A series of registers are available in the Intel FWH to provide software read- and write-locking and GPI feedback. Also available are the set of control registers for controlling and gathering random numbers. These registers are accessible through standard addressable memory space (see the following table). ...

Page 24

... Intel 82802AB/AC Firmware Hub Table 5. Intel Firmware Hub Register Configuration Map Memory Address FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFB70002h FFB60002h FFB50002h FFB40002h FFB30002h FFB20002h FFB10002h FFB00002h FFBC0100h FFBC015Fh FFBC0160h FFBC0161h * Assumes RNG is present and not disabled. 24 Mnemonic ...

Page 25

... Lock-Down, Write Lock, Data 2 Data 1 Data ® Intel 82802AB/AC Firmware Hub Resulting block state . (1) Full access Write locked. Default state at power- up Locked open (full access locked down). Write-locked down. Read locked. Read and write locked. Read-locked down. Read- and write-locked down. 25 ...

Page 26

... General-Purpose Input Register This register reads the status of the FGPI [4:0] pins on the Intel FWH. Since this is a pass-through register, there is no default value, only the state of the pins at power-up. 4.9.2.1. GPI_REG — General-Purpose Input Register ...

Page 27

... RNG data register. The advantages of random numbers over pseudo-random numbers as well as a brief overview of the simple mathematics of testing RNGs are discussed superficially in the companion document, The Intel Platform RNG Tech Brief, which is available online. ...

Page 28

... Detecting and Initializing the RNG Device Before any process attempts to read random data directly from the Intel Firmware Hub RNG device, it should execute a process to verify that a supported RNG device is available for use, enable the device, and verify the correct functionality. This initialization process is described in a following subsection. ...

Page 29

... FWH protocol supports FWH devices, the BIOS support, bus loading or the attaching bridge may limit this number. Note that, regardless of the number of FWH components, the maximum “window” of the FWH array visible at one time (for Intel boot device must have an ID (as determined by ID [0:3 For clarity advisable that subsequent devices use incremental numbering ...

Page 30

... Mapping FWH Devices onto Memory Map There available memory space devoted to the FWH. Therefore, the Intel ICH has the ability to select which FWH device maps into each region of the system address space. In the existing Intel ICH, the address map is broken up into eight 512-KB segments. The BIOS Select Register in the Intel ICH is a 32-bit register that contains the needed mapping information, thereby determining which FWH receives requests from which portion of the address map ...

Page 31

... Register command in cases where multiple blocks are erased before full status is checked error is detected, clear the Status Register before attempting Block Erase retry or other error recovery. Error ® Intel 82802AB/AC Firmware Hub Command Comments Data = 20h Erase Setup Addr = Within Block to Be Erased Erase ...

Page 32

... Intel 82802AB/AC Firmware Hub 32 This page left intentionally blank R Datasheet ...

Page 33

... CC may overshoot to +14.0 V for periods of <20 ns allowed for a maximum cumulative period of 80 hours. HH Parameter Notes Min 3.0 ® Intel 82802AB/AC Firmware Hub *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. ...

Page 34

... Intel 82802AB/AC Firmware Hub 5.2.1. Interface DC Input/Output Specifications Table 8. Intel FWH Interface DC Input/Output Specifications Symbol V Input high voltage IH V INIT# input high voltage IH (INIT#) V Input low voltage IL I Input leakage current IL V Output high voltage OH V Output low voltage OL C Input pin capacitance ...

Page 35

... No internal operations in progress. VCC = VCC Max, CLK MHz Any internal operation in progress, IOUT = 0mA V ≥ 3.0-3 11.4-12 0.1 V per the PCI output memory core + ® Intel 82802AB/AC Firmware Hub Min. Max. Units 3.0 3.6 V 11.4 12.6 V 1.5 V 1.5 V 100 µ 200 µ and V specifications of Table 8 ...

Page 36

... Intel 82802AB/AC Firmware Hub 5.2.2. Interface AC Input/Output Specifications Table 10. Intel FWH Interface AC Input/Output Specifications Symbol Parameter Ioh(AC) Switching current High (Test point) Iol(AC) Switching current Low (Test point) Icl Low clamp current Ich High clamp current slewr Output rise slew rate ...

Page 37

... R 5.2.3. Intel FWH Interface AC Timing Specifications 5.2.3.1. Clock Specification Table 11. Clock Specification Symbol tcyc CLK cycle time thigh CLK high time tlow CLK low time - CLK slew rate - RST# or INIT# slew rate Note: 1. PCI components must work with any clock frequency between nominal DC and 33 MHz. ...

Page 38

... Intel 82802AB/AC Firmware Hub 5.2.3.2. Signal Timing Parameters Table 12. Signal Timing Parameters Symbol PCI Symbol TCHQV t val TCHQX t on TCHQZ t off TAVCH t su TDVCH TCHAX t h TCHDX TVSPL t rst TCSPL t rst-clk TPLQZ t rst-off Note: 1. Minimum and maximum times have different loads. See PCI spec. ...

Page 39

... There will be a 20-µs reset latency if a reset procedure is performed during a programming or erase operation. Datasheet CLK Value Units Notes RST# ( Parameter , this specification is not applicable.) CC ® Intel 82802AB/AC Firmware Hub V_th V_test V_tl T_su T_h Inputs V_max Valid Min. Max. Unit Notes 100 ...

Page 40

... Intel FWH Interface Cycles When the Intel FWH interface is active, information is transferred to and from the FWH by a series of “fields,” where each field contains 4 bits of data. Many fields are one clock cycle in length but can be of variable length, depending upon the nature of the field. Field sequences and contents are strictly defined for read and write operations. The following tables list the field sequences for read and write cycles. Addresses in this section refer to addresses as seen from the FWH’ ...

Page 41

... The FWH will only support single-byte transfers. 1111 IN In this clock cycle, the master (Intel ICH) has driven the then float bus to all 1s and then floats the bus, prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” ...

Page 42

... This field is the most-significant nibble of the data byte. 1111 IN In this clock cycle, the master (Intel ICH) has driven then float the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” ...

Page 43

... During FWH operations, the Intel FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: • Address out of range: The Intel FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For a 4-Mbit density, the most- significant bit (FWH3) in the third address field also will be ignored ...

Page 44

... Abort Operations FWH4 active (low) indicates either that a START cycle will eventually occur or that an abort is in progress. In either case, if FWH4 is asserted, the Intel FWH will “immediately” tri-state its outputs and the FWH state machine will reset. During a write cycle, there is a possibility that an internal flash write or erase operation is in progress (or has just been initiated) ...

Page 45

... RNG Statistical Characteristics # Sym B2 Fractional probability of excess 1s AC Auto correlation coefficient FOM Figure of merit Note: 1. Sampled, not 100% tested. Figure 12. Intel FWH Output Timing Parameters (Valid Output Data) (Float Output Data) Datasheet Parameter Parameter CLK V_test T_val FWH[3:0] FWH[3:0] T_off ® ...

Page 46

... Intel 82802AB/AC Firmware Hub Figure 13. Intel FWH Input Timing Parameters CLK FWH[3:0] (Valid Input Data) 46 V_test T_su T_h Inputs Valid R V_th V_tl V_max Datasheet ...

Page 47

... Intel 82802 should be expected that a modest current will be drawn. (See the pin descriptions in Table 1 for further information.) The following information applies only to the Intel regarding the FWH mode (i.e., the standard operating mode) is provided in earlier chapters of this document 6.2. Bus Operation All A/A mux bus cycles can be conformed to operate on most automated test equipment and PROM programmers ...

Page 48

... Certain specifications differ from the previous sections, when programming in the A/A Mux mode. The following subsections provide this data. Any information not provided here is not specific to the A/A Mux mode. Refer to Section 5 of this document and use the Intel FWH mode specifications. 48 ...

Page 49

... OE# low to output delay RST# high to row address setup OE# low to output in low Z OE# high to output in high Z Output hold from OE# high – t after the rising edge of R/C# without affecting t CHQV GLQV CC ® Intel 82802AB/AC Firmware Hub Notes Min. Max. , this 100 Notes Min. ...

Page 50

... Intel 82802AB/AC Firmware Hub Figure 14. A/A Mux Read Timing Diagram V IH ADDRESSES ( R/C# ( OE# ( DATA (D/ WE# ( RP# ( Row Address Column Address Stable Stable High Next Address Stable x R7 R10 R11 High Z Data Valid Datasheet ...

Page 51

... R/C# high setup to WE# high V setup to WE# high PP1,2 Write recovery before read WE# high to RY/BY# going low V hold from valid SRD, RY/BY# high PP1,2 and D for block erase or program or other commands ® Intel 82802AB/AC Firmware Hub Notes Min. Max. Units 1 µs 100 ...

Page 52

... Intel 82802AB/AC Firmware Hub Figure 15. A/A Mux Write Timing Diagram ADDRESSES ( R/C# ( WE# ( OE# ( DATA (D/ RY/BY# ( RP# ( PPH1 Note power-up and stand- Write block erase or program setup C Write block erase confirm or valid address and data D Automated erase or program delay E Read status register data ...

Page 53

... Ibaraki-ken 305 Japan Phone: (81) 298 47 8522 South America Intel Semicondutores do Brazil Rue Florida, 1703-2 and CJ22 CEP 04565-001 Sao Paulo-SP Brazil Phone: (55) 11 5505 2296 For more information To learn more about Intel Corporation, visit our site on the World Wide Web at www.intel.com ...

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