LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet
LPC47M142-NC
Specifications of LPC47M142-NC
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LPC47M142-NC Summary of contents
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... Pin Enhanced Super I/O Controller with an LPC Interface and USB Hub 3.3 Volt Operation (5 Volt Tolerant) LPC Interface ACPI 1.0 Compliant Fan Control Fan Speed Control Outputs - - Fan Tachometer Inputs Programmable Wake-up Event Interface PC98, PC99 Compliant Dual Game Port Interface ...
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Upstream and Downstream Ports - Compliant with USB Spec. version 1.1 - Programmable USB Manufacturer ID, Product ID and Device Rev. Number - Number of active ports programmable or selectable via jumpers - Powered by ...
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... The LPC47M14x 3.3V (5V tolerant) PC99 compliant Super I/O controller with an LPC interface and a standalone USB hub designed to be compatible with a family of Super I/O Controllers (LPC47M13x, LPC47M14x, and LPC47M15x). To the interested reader, the LPC47M15x offers hardware monitoring capabilities. hundred pins of all these packages are completely pin compatible and offer the designer added flexibility in their board designs ...
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PIN LAYOUT ..........................................................................................................................................................8 2 PIN CONFIGURATION...........................................................................................................................................9 3 DESCRIPTION OF PIN FUNCTIONS...................................................................................................................10 3 UFFER YPE ESCRIPTIONS 3 INS HAT EQUIRE XTERNAL 4 BLOCK DIAGRAM ...............................................................................................................................................16 5 POWER FUNCTIONALITY...................................................................................................................................17 5.1 VCC P ..................................................................................................................................................17 OWER ...
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Default Reset Conditions ...................................................................................................................... 105 6.13.9 Latches On Keyboard and Mouse IRQs ............................................................................................... 108 6.13.10 Keyboard and Mouse PME Generation ................................................................................................ 109 6.14 GENERAL PURPOSE I/O.......................................................................................................................... 110 6.14.1 GPIO Pins............................................................................................................................................. 110 6.14.2 Description............................................................................................................................................ 111 6.14.3 GPIO Control ........................................................................................................................................ 112 ...
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Table 23 – Result Phase Table ..................................................................................................................................52 Table 24 – Verify Command Result Phase Table ......................................................................................................53 Table 25 – Typical Values for Formatting...................................................................................................................55 Table 26 – Interrupt Identification...............................................................................................................................56 Table 27 – Drive Control Delays (ms) ........................................................................................................................57 Table 28 – Effects ...
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FIGURE 1 – LPC47M14X BLOCK DIAGRAM...........................................................................................................16 FIGURE 2 – LPC47M14X CLOCK GENERATOR .....................................................................................................24 FIGURE 3 – MPU-401 MIDI INTERFACE..................................................................................................................73 FIGURE 4 – MPU-401 INTERRUPT ..........................................................................................................................76 FIGURE 5 - MIDI DATA BYTE EXAMPLE ...................................................................................................................77 FIGURE 6 – KEYBOARD LATCH ............................................................................................................................108 FIGURE ...
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PIN LAYOUT 1 GP40/DRVDEN0 2 GP41/DRVDEN1 3 nMTR0 4 nDSKCHG 5 nDS0 6 CLKI32 7 VSS 8 nDIR 9 nSTEP 10 nWDATA 11 nWGATE 12 nHDSEL 13 nINDEX 14 nTRK0 15 nWRTPRT 16 nRDATA 17 GP42/nIO_PME 18 VTR 19 ...
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PIN CONFIGURATION PIN # NAME PIN # 1 GP40/DRVDEN0 33 2 GP41/DRVDEN1 34 3 nMTR0 35 4 nDSKCHG 36 5 nDS0 37 6 CLKI32 38 7 VSS 39 8 nDIR 40 9 nSTEP 41 10 nWDATA 42 11 nWGATE ...
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DESCRIPTION OF PIN FUNCTIONS NAME QFP PIN # 23:20 Multiplexed Command, Address, Data [3:0] 24 Frame 25 Encoded DMA Request 26 PCI Reset 27 Power Down 29 PCI Clock 30 Serial IRQ 6 32.768KHz Trickle Clock Input 19 14.318MHz ...
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QFP NAME PIN # 12 Head Select 8 Step Direction 9 Step Pulse 4 Disk Change 5 Drive Select 0 3 Motor Write Protected 14 Track 0 13 Index Pulse Input 1 General Purpose I/O/Drive Density Select ...
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QFP NAME PIN # 75 Port Data 7 77 Printer Selected Status 78 Paper End 79 Busy 80 Acknowledge 81 Error 82 Autofeed Output 83 Strobe Output 56 Keyboard Data 57 Keyboard Clock 58 Mouse Data 59 Mouse Clock 63 ...
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QFP NAME PIN # General Purpose I/O 32 /Joystick 1 Button 1 General Purpose I/O 33 /Joystick 1 Button 2 General Purpose I/O 34 /Joystick 2 Button 1 General Purpose I/O 35 /Joystick 2 Button 2 General Purpose I/O 36 ...
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An external pullup resistor is required to move the base IO address for configuration to 0x04E. Note 9: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs after an ...
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PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS The following pins require external pullup resistors: KDAT KCLK MDAT MCLK GP36/KBDRST if KBDRST function is used GP37/A20M if A20M function is used GP20/P17 If P17 function is used GP21/P16 if P16 function ...
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BLOCK DIAGRAM CLK32 CLOCK GEN CLOCKI SER_IRQ SERIAL PCI_CLK IRQ LAD[3:0] LPC LFrame Bus Interface LDRQ PCI_RESET LPCPD IO_PME* Power Mgmt IO_SMI* GP1[0:7]* GP2[0:2,4:7]* General GP3[0:7]*, GP4[0:3]* Purpose I/O GP5[0:7]*, GP6[0:1]* ICLK CLOCK GEN OCLK PD1+ PD1- PD2+ PD2- ...
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POWER FUNCTIONALITY The LPC47M14x has three power planes: VCC, VTR, and VREF. 5.1 VCC POWER The LPC47M14x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the “Operational Description” Section and the “Maximum Current Values” ...
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INTERNAL PWRGOOD An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as V cycles on and off. When the internal PWRGOOD signal is “1” (active LPC47M14x host interface ...
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Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are powered by VTR so that the pins are always forced low when not used. GP42 is the nIO_PME pin, which is active ...
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FUNCTIONAL DESCRIPTION 6.1 SUPER I/O REGISTERS The address map, shown below in Table 1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, ...
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LPC INTERFACE The following sub-sections specify the implementation of the LPC bus. 6.3.1 LPC Interface Signal Definition The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal ...
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The LPC47M14x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend ...
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If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M14x has protection mechanisms to complete the ...
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USB HUB FUNCTIONAL DESCRIPTION The USB Hub Block implements one upstream port and up to four downstream ports. The internal address/data/control connection is provided for programming by BIOS the USB Vendor ID, Product ID, Device Revision Number and number ...
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Resume. 6.4.1 USB Downstream Port Selection The LPC47M14x USB Hub has the ability to program, via BIOS, control register access or through external PIN strapping options, the number of Down Stream Ports that are available to the User. There is ...
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OFFSET FIELD PROGRAMMABLE 5 bPwrOn2PwrGood 6 bHubContrCurrent 7 DeviceRemovable Variable PortPwrCtrlMask 6.5 FLOPPY DISK CONTROLLER The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, ...
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The Floppy Disk Controller contains eight internal registers, which facilitate the interfacing between the host microprocessor and the disk drive. Table 3 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The ...
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INT PENDING RESET 0 COND. BIT 0 DIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE ...
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Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of ...
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BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy ...
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Table 6 – Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration ...
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DRIVE RATE DRT1 DRT0 Drive Rate Table (Recommended) Note 1: The DRATE and DENSEL values are ...
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Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to ...
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CRC. Reads require the host to remove the remaining data so that the result phase may be entered. FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES ...
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This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS DATA RATE SELECT These bits control the data rate of the ...
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Should be set to a logical "0" PS/2 Model 30 Mode 7 RESET N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 9 for the ...
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BIT NO. SYMBOL BIT NO. SYMBOL SMSC DS – LPC47M14X NAME End of ...
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BIT NO. SYMBOL 1,0 DS1,0 RESET There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR, and a reset ...
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Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be ...
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RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating ...
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SYMBOL NAME MT Multi-Track Selector N Sector Size Code This specifies the number of bytes in a sector. If this parameter is NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK ...
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SYMBOL NAME WGATE Write Gate 6.5.3 Instruction Set PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – LPC47M14X DESCRIPTION Alters timing ...
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PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W MT MFM ...
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PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command ...
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PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W 0 Result R 1 SMSC DS – LPC47M14X VERIFY DATA ...
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PHASE R/W D7 Command Execution for W Each Sector Repeat Result PHASE R/W D7 Command Execution PHASE R/W ...
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PHASE R/W D7 Command Result R PHASE R/W D7 Command Execution PHASE R/W D7 Command Execution W PHASE R/W D7 Command ...
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PHASE R/W D7 Command Execution Result PHASE R/W D7 Command W OW PHASE R/W D7 Command W Result R PHASE R/W Command W LOCK Result returned ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An ...
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DATA ADDRESS MARK TYPE SK BIT ENCOUNTERED VALUE 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data Read Deleted Data This command is ...
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This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read ...
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The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Drives 3.5" Drives GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) ...
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The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there ...
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The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. ...
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DIR Head Step Direction Control RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The Relative Seek command differs from the Seek command in that it steps the ...
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For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head ...
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ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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Bit 4,5 Reserved Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt. INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine ...
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FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT 3 BIT 2 BIT 1 BIT LINE CONTROL REGISTER (LCR) Address Offset = 3H, ...
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Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in ...
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This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1) The TXD is set to the Marking State(logic "1"). 2) The receiver Serial Input (RXD) ...
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XMIT FIFO. Bit read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It ...
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BRG is a 1.8462 MHz clock. Table 31 shows the baud rates possible. Effect Of The Reset on Register File The Reset Function (details the effect of the Reset input on each of the registers of the ...
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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, ...
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REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO ...
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REGISTER ADDRESS* ADDR = 6 MODEM Status Register ADDR = 7 Scratch Register (Note 4) ADDR = 0 Divisor Latch (LS) DLAB = 1 ADDR = 1 Divisor Latch (MS) DLAB = 1 *DLAB is Bit 7 of the Line ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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INFRARED INTERFACE The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. ...
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MPU-401 MIDI UART 6.8.1 Overview Serial Port 3 is used exclusively in the LPC47M14x as an MPU-401-compatible MIDI Interface. The LPC47M14x MPU-401 hardware includes a Host Interface, an MPU-401 command controller, configuration registers, and a compatible UART (FIGURE 3). ...
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The run-time registers in the MPU-401 Host Interface are shown below in Table 34. Table 34 – MPU-401 Host Interface Registers REGISTER NAME MIDI DATA MPU-401 I/O Base Address STATUS MPU-401 I/O Base Address + 1 COMMAND MPU-401 I/O Base ...
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Table 37 – MIDI Receive Buffer Empty Status Bit STATUS PORT Bit 6 – MIDI Transmit Busy Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 38) ...
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MIDI_IN MIDI RX DATA BYTE N 4 MIDI RX CLOCK 1 DATA READY 3 IRQ 2 nREAD 1 Note DATA READY represents the Data Ready bit B0 in the 16C550A UART Line Status Register. 2 Note nREAD represents host read ...
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MIDI Data port read buffer. 6.8.6 MIDI UART Overview The UART is used to transmit and receive MIDI protocol data from the MIDI Data port in the Host Interface (see ...
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PARALLEL PORT The LPC47M14x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration ...
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HOST CONNECTOR PIN NUMBER 1 83 2-9 68- (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ...
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The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. BIT 6 nACK - ACKNOWLEDGE The ...
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ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP ...
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The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read ...
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The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used ...
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ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional ...
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ECP IMPLEMENTATION STANDARD This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description ...
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The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ...
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ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register ...
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CFIFO (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the ...
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Returns the value of the interrupt to determine possible conflicts. BIT [5:3] Parallel Port IRQ (read-only) to Table 45B BITS [2:0] Parallel Port DMA (read-only) to Table 45C ECR (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This ...
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R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression ...
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The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting ...
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FIFO in a single burst. Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes ...
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Register Behavior Table 47 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 47 shows, two ...
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Table 48 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled “Unchanged.” Table 48 – State of System Pins in Auto Powerdown SYSTEM PINS LAD[3:0] LDRQ# LPCPD# LFRAME# PCI_RESET# PCI_CLK SER_IRQ ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations: 1) The transmitter enters ...
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SERIAL IRQ The LPC47M14x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams For SER_IRQ Cycle A) Start Frame ...
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SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame. 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving ...
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System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical ...
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INTERRUPT GENERATING REGISTERS The LPC47M14x contains on-chip Interrupt Generating Registers to enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2 as shown below, are located in the Logical Device A ...
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KEYBOARD CONTROLLER DESCRIPTION The LPC47M14x is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on ...
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The LPC47M14x LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table 50 shows how ...
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A general purpose P21 is used as a software controlled Gate A20 or user defined output. 8042 PINS The 8042 functions P17, P16 and P12 are implemented true 8042 part. Reference the 8042 spec for all timing. ...
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Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output ...
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Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1. This register is used to support the alternate reset ...
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P20 P92 Bit 0 Note: When Port 92 is writes are ignored and return undefined Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. ...
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The implementation of the latches on the keyboard and mouse interrupts is shown below. 8042 8042 The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0. These bits are defined as follows: Bit[4]: ...
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Keyboard and Mouse PME Generation The LPC47M14x sets the associated PME Status bits when the following conditions occur: Keyboard Interrupt Mouse Interrupt • Active Edge on Keyboard Data Signal (KDAT) • Active Edge on Mouse Data Signal (MDAT) These ...
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GENERAL PURPOSE I/O The LPC47M14x provides a set of flexible Input/Output control functions to the system designer through the 37 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them ...
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Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in ...
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Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the “Runtime Registers” section of this specification. Each GPIO port may be configured as either an input or an output. ...
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Note: FIGURE 8 is for illustration purposes only and is not intended to suggest specific implementation details. Note: When the following functions are selected, the associated GPIO pins have bi-directional functionality: P12, P16, P17 and game port x-axis and y-axis ...
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PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in the MSC_STS status register that is set on both edges. The corresponding bits in the PME and ...
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GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits. Status bits are cleared on a write of ‘1’. See the “Runtime Registers” section for more information. The configuration register for ...
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PME SUPPORT The LPC47M14x offers support for power management events (PMEs), also referred System Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the ...
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There is a bit in the PME Status Register 3 to show the status of the internal “group” SMI signal in the PME logic (if bit 5 of the SMI_EN2 register is set). This bit, DEVINT_STS bit 3 ...
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SPEKEY_EN bit (see following sub-section). The state machine will reset if there is a period where the clock remains high for more than one keyboard clock period (115-145usec) in the middle of the transmission (i.e., before clock 11). ...
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The FAN1 and FAN2 Registers are located at 0x56 and 0x57 from base I/O in Logical Device A. The bits are defined below. See the register description in the “Runtime Registers” section. Fan x Clock Select Bit, D7 The Fan ...
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Fan Tachometer Input Clock Source for Counter The counter is reset by the rising edge of each pulse (and by writing the preload register). The counter does not wrap reaches 0xFF, it remains at 0xFF until it is ...
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Programmable 32 kHz The following tables show examples of the desired functionality. Counts are based on 2 pulses per revolution tachometer outputs with a default divisor of 2. TERM 1 FOR “DIVIDE BY 2” (DEFAULT) IN TIME PER REVOLUTION RPM ...
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SECURITY FEATURE The following register describes the functionality to support security in the LPC47M14x. 6.18.1 GPIO Device Disable Register Control The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 ...
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RC constant (TIMA,B) pins to zero when the RC constant (TIMA,B) inputs reach 2/3 of VREF as shown. VREF is the voltage on pin 44, which is either 5V or 3.3V. See the “VREF Pin “ section. ...
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Register Location: <GAME_PORT>+0h Default Value: 00h Attribute: Read-Only Size: 8-bits D7 D6 Button #2 Button #1 Button #2 Joystick 2 Joystick 2 Joystick 1 (J2B2) (J2B1) The game port register is a read-only register. However, writing to the game port ...
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RUNTIME REGISTERS The following registers are runtime registers in the LPC47M14x. They are located at the address programmed in the Base I/O Address in Logical Device A (also referred to as the PME register) at the offset shown. These ...
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REGISTER OFFSET HARD (hex) RESET TYPE ...
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REGISTER OFFSET HARD (hex) RESET TYPE R/W - 60- Note 1: This register is read-only when GP43 register bit [3: ...
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REG OFFSET NAME PME_STS1 Default = 0x00 on VTR POR PME_STS2 Default = 0x00 on VTR POR PME_STS3 Default = 0x00 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 04 PME Wake Status Register 1 This register indicates the ...
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REG OFFSET NAME PME_STS4 Default = 0x00 on VTR POR (Note 6) PME_STS5 Default = 0x00 on VTR POR (Note 6) N/A SMSC DS – LPC47M14X (hex) DESCRIPTION 07 PME Wake Status Register 4 This register indicates the state of ...
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REG OFFSET NAME PME_EN1 Default = 0x00 on VTR POR PME_EN2 Default = 0x00 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 0A PME Wake Enable Register 1 This register is used to enable individual LPC47M14x PME wake sources ...
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REG OFFSET NAME PME_EN3 Default = 0x00 on VTR POR PME_EN4 Default = 0x00 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 0C PME Wake Status Register 3 This register is used to enable individual LPC47M14x PME wake sources ...
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REG OFFSET NAME PME_EN5 Default = 0x00 on VTR POR N/A SMI_STS1 Default = 0x02 on VTR POR Bit 1 is set to ‘1’ on VCC POR, VTR POR, HARD RESET and SOFT RESET SMI_STS2 Default = 0x00 on VTR ...
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REG OFFSET NAME SMI_STS3 Default = 0x00 on VTR POR SMI_STS4 Default = 0x00 on VTR POR (Note 6) SMI_STS5 Default = 0x00 on VTR POR N/A SMI_EN1 Default = 0x00 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION ...
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REG OFFSET NAME SMI_EN2 Default = 0x00 on VTR POR SMI_EN3 Default = 0x00 on VTR POR SMI_EN4 Default = 0x00 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 17 SMI Enable Register 2 This register is used to ...
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REG OFFSET NAME SMI_EN5 Default = 0x00 on VTR POR N/A MSC_STS Default = 0x00 on VTR POR N/A Force Disk Change Default = 0x01 on VCC POR SMSC DS – LPC47M14X (hex) DESCRIPTION 1A SMI Enable Register 5 This ...
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REG OFFSET NAME Floppy Data Rate Select Shadow UART1 FIFO Control Shadow UART2 FIFO Control Shadow SMSC DS – LPC47M14X (hex) DESCRIPTION 1F Floppy Data Rate Select Shadow Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 (R) Bit[2] ...
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REG OFFSET NAME Device Disable Register Read/Write when Default = 0x00 GP43 register VTR POR bits[3: GP43 pin = 0 GP43 register bits[3:2] ≠ 01 READ-ONLY When GP43 register bits[3:2] =01 AND GP43 GP10 Default = 0x01 on ...
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REG OFFSET NAME GP11 Default = 0x01 on VTR POR GP12 Default = 0x01 on VTR POR GP13 Default = 0x01 on VTR POR GP14 Default = 0x01 on VTR POR GP15 Default = 0x01 on VTR POR SMSC DS ...
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REG OFFSET NAME GP16 Default = 0x01 on VTR POR GP17 Default = 0x01 on VTR POR GP20 Default = 0x01 on VTR POR GP21 Default =0x01 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 29 General Purpose I/0 ...
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REG OFFSET NAME GP22 Default =0x01 on VTR POR N/A GP24 Default = 0x01 on VTR POR GP25 Default = 0x01 on VTR POR GP26 Default = 0x01 on VTR POR GP27 Default = 0x01 on VTR POR SMSC DS ...
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REG OFFSET NAME GP30 Default = 0x01 on VTR POR GP31 Default = 0x01 on VTR POR GP32 Default = 0x01 on VTR POR Default = 0x00 on VCC POR and Hard Reset (Note 3) GP33 Default = 0x01 on ...
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REG OFFSET NAME GP35 Default = 0x04 on VTR POR, VCC POR and Hard Reset (Note 3) GP36 Default = 0x01 on VTR POR GP37 Default = 0x01 on VTR POR GP40 Default =0x01 on VTR POR GP41 Default =0x01 ...
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REG OFFSET NAME GP42 Default =0x01 on VTR POR GP43 Default = 0x01 on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and Hard Reset GP50 Default = 0x01 on VTR POR SMSC DS – LPC47M14X (hex) ...
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REG OFFSET NAME GP51 Default = 0x01 on VTR POR GP52 Default = 0x01 on VTR POR GP53 Default = 0x00 on VTR POR, VCC POR and Hard Reset (Note 3) GP54 Default = 0x01 on VTR POR SMSC DS ...
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REG OFFSET NAME GP55 Default = 0x01 on VTR POR GP56 Default = 0x01 on VTR POR GP57 Default = 0x01 on VTR POR GP60 Default = 0x01 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 44 General Purpose ...
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REG OFFSET NAME GP61 Default = 0x01 on VTR POR N/A N/A GP1 Default = 0x00 on VTR POR GP2 Default = 0x00 on VTR POR GP3 Default = 0x00 on VTR POR Bits 2 and 3 are reset on ...
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REG OFFSET NAME GP5 Default = 0x00 on VTR POR Bit 3 is reset on VCC POR, Hard Reset and VTR POR GP6 Default = 0x00 on VTR POR N/A N/A N/A INT_GEN1 Default = 0xFF on VCC POR and ...
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REG OFFSET NAME FAN1 Default = 0x00 on VTR POR FAN2 Default = 0x00 on VTR POR SMSC DS – LPC47M14X (hex) DESCRIPTION 56 FAN Register 1 Bit[0] Fan Control (R/W) 1=FAN1 pin is high 0=bits[6:1] control the duty cycle ...
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REG OFFSET NAME Fan Control Default = 0x50 on VTR POR Fan1 Tachometer Register Default = 0x00 on VTR POR Fan2 Tachometer Register Default = 0x00 on VTR POR Fan1 Preload Register Default = 0x00 on VTR POR SMSC DS ...
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REG OFFSET NAME Fan2 Preload Register Default = 0x00 on VTR POR LED1 Default = 0x00 on VTR POR LED2 Default = 0x00 on VTR POR Keyboard Scan Code Default = 0x00 on VTR POR N/A Note 1: If the ...
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Note 9: If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1 in the PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register. ...
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CONFIGURATION The Configuration of the LPC47M14x is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47M14x is designed for motherboard applications in which the resources required by their components are known. With ...
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CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1) Enter Configuration Mode 2) Configure the Configuration Registers 3) Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key ...
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SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 61 – LPC47M14x Configuration Registers Summary INDEX TYPE HARD RESET 0x02 W 0x00 0x03 ...
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INDEX TYPE HARD RESET LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x70 R/W 0x00 0xF0 R/W 0x00 LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) 0x30 R/W - 0x60, R/W 0x00, ...
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LOGICAL DEVICE C CONFIGURATION REGISTERS (USB Hub) 0x30 R/W 0x00 0xF0 R/W - 0xF1 R/W - 0xF2 R/W - 0xF3 R/W - 0xF4 R/W - 0xF5 R/W - 0xF6 R/W - 0xF7 R/W - Note 1: CR22 bit 5 is ...
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REGISTER ADDRESS Device ID - 0x20 R Hard wired Default = 0x5F on VCC POR, VTR POR, SOFT RESET and HARD RESET Device Rev 0x21 R Hard wired = Current Revision PowerControl 0x22 R/W Default = 0x00 on VCC POR, ...
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REGISTER ADDRESS Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0x2E (Sysopt=0) =0x4E (Sysopt=1) on VCC POR and HARD RESET Configuration 0x27 Address Byte 1 Default = 0x00 on VCC POR and HARD RESET Default = 0x00 ...
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REGISTER ADDRESS TEST 3 0x2F R/W Default = 0x00, on VCC POR and VTR POR Note 1: CR22 Bit 5 is reset by VTR POR only. Note 2: To allow the selection of the configuration address to a user defined ...
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LOGICAL DEVICE REGISTER Interrupt Select Defaults : 0x70 = 0x00 or 0x06 (Note 3) on VCC POR, VTR POR, HARD RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, HARD RESET and SOFT RESET DMA Channel Select ...
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Table 65 – I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE 0x00 FDC 0x60,0x61 0x01 Reserved 0x02 Reserved 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 1 0x60,0x61 0x05 Serial Port 2 0x60,0x61 0x06 Reserved 0x07 KYBD ...
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Table 65 – I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE 0x0B MPU-401 0x60,0x61 Config. Config. Port 0x26, 0x27 Port (Note 2) 0x0C USB Hub Note 1: This chip uses address bits [A11:A0] to decode the ...
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NAME REG INDEX DMA Channel 0x74 (R/W) Select Default=0x02 or 0x04 (Note 1) on VCC POR, VTR POR, HARD RESET and SOFT RESET Note: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers are not affected by ...
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Table 68 – Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD0 0xF4 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET FDD1 0xF5 R/W Table 69 – Parallel Port, Logical ...
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Table 70 – Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET Note 1: To properly share ...
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Table 71 – Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on VCC POR, VTR POR and HARD RESET IR Half Duplex 0xF2 Timeout Default = ...
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Table 72 – KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET Bits[6:5] reset on VTR POR only 0xF1 - 0xFF Table 73 ...
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NAME REG INDEX INT_G Default = 0x00 0xF1 on VCC POR, VTR R/W POR, HARD RESET and SOFT RESET 0xF2- 0xFF Note: The registers located in Logical Device A are runtime registers. Note 1: SMSC Reserved registers have read/write capability. ...
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NAME REG INDEX IdVendor_Low 0xF1 Default=0x24 R/W on VTR POR IdVendor_High 0xF2 Default=0x04 R/W on VTR POR IdProduct_Low 0xF3 Default=40 R/W on VTR POR IdProduct_High 0xF4 Default=01 R/W on VTR POR BcdDevice_Low 0xF5 Default=0x00 R/W on VTR POR BcdDevice_High 0xF6 ...
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Table 76 – HubControl_1 Register Definition HubControl_1 RESET=0x00 INDEX=0xF7 BIT NAME R/W 7 NHubReset R/W 6 Strp1 R/W 5 Strp0 R/W 4:1 Reserved R 0 Ganged R/W PWR Note 1: When the specified USB Down Stream Ports are disabled via ...
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OPERATIONAL DESCRIPTION 9.1 MAXIMUM GUARANTEED RATINGS Operating Temperature Range........................................................................................................................... 0 Storage Temperature Range............................................................................................................................-55 Lead Temperature Range ............................................................................................... Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground................................................................................................. V Negative Voltage on any pin, with respect ...
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PARAMETER IO8 Type Buffer Low Output Level High Output Level Leakage Current O8 Type Buffer Low Output Level High Output Level OD8 Type Buffer Low Output Level Leakage Current O12 Type Buffer Low Output Level High Output Level IO12 Type ...
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PARAMETER IOP14 Type Buffer Low Output Level High Output Level Leakage Current IOD16 Type Buffer Low Output Level Leakage Current O24 Type Buffer Low Output Level High Output Level Backdrive Protect/ChiProtect (All signal pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#, USB+, ...
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PARAMETER IOUSB Output Levels: Static Output Low (Note 3) Static Output High (Note 3) Output Signal Crossover Voltage (Note 3) V Supply Current Active CC Trickle Supply Voltage V Supply Current Active TR Reference Voltage V Supply Current Active REF ...
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CAPACITANCE T = 25° 1MHz PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance Input Capacitance for the USB HUB Interface Pins (Note 1) Downstream Port Upstream Port (w/o cable) Note 1: The input capacitance of a ...
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TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. PD+[1:4] (Low-Speed) Note 1: Total capacitance of load with cable. SMSC DS – LPC47M14X CAPACITANCE TOTAL (pF) NAME SER_IRQ LAD# [3:0] LDRQ# nDIR nSTEP ...
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NAME DESCRIPTION t1 Vcc Slew from 2. Vcc Slew from 0V to 2.7V t3 All Host Accesses After Powerup ...
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PARAMETER Differential Rise/Fall Time Matching Drive Output Impedance DRIVER CHARACTERISTICS (Low-Speed) Transition Time: Rise Time Fall Time Differential Rise/Fall Time Matching DATA TRANSFER TIMINGS Full Speed Data Rate TDRATE Frame Interval TFRAME Clock Period TPERIOD Source Jitter Total (including frequency ...
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Differential Data Lines FIGURE 10 – DATA SIGNAL RISE AND FALL TIME Full Speed 20ns at C Note: The output impedance of the buffer with a series resistance (Rs Ω Ω . Low-Speed Buffer ...
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T PERIOD Differential Data Lines T PERIOD Differential Data Lines FIGURE 15 – DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH T PERIOD Differential Data Lines FIGURE 16 – RECEIVER JITTER TOLERANCE SMSC DS – LPC47M14X Crossover Points Consecutive Transitions ...
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CLOCKI NAME t1 Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32KHZ t2 Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown ...
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CLK Output Delay Tri-State Output FIGURE 20 – OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME t1 CLK to Signal Valid Delay – Bused Signals t2 Float to Active Delay t3 Active to Float Delay CLK Input FIGURE 21 – INPUT ...
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PCI_CLK LFRAME# LAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 PCI_CLK LFRAME# LAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 SMSC DS – LPC47M14X Address Data TAR FIGURE 22 – I/O WRITE Address TAR Sync=0110 FIGURE 23 – ...
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PCI_CLK LDRQ# FIGURE 24 – DMA REQUEST ASSERTION THROUGH LDRQ# PCI_CLK LFRAME# LAD[3:0] Start C+D CHL Size Note: L1=Sync of 0000 PCI_CLK LFRAME# LAD[3:0] Start C+D Note: L1=Sync of 0000 SMSC DS – LPC47M14X Start MSB TAR Sync=0101 FIGURE 25 ...
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FIGURE 27 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) NAME t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after STEP# t4 nSTEP Cycle Time ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 28 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE NAME t1 nWAIT Asserted to nWRITE Asserted (Note 1) t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWAIT Asserted to PDATA Invalid (Note 1) ...
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PD<7:0> DATASTB ADDRSTB nWAIT FIGURE 29 – EPP 1.9 DATA OR ADDRESS READ CYCLE NAME t1 nWAIT Asserted to nWRITE Deasserted t2 nWAIT Asserted to nWRITE Modified (Notes 1,2) t3 nWAIT Asserted to PDATA Hi-Z (Note 1) t4 Command ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 30 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME t1 Command Deasserted to nWRITE Change t2 Command Deasserted to PDATA Invalid t3 PDATA Valid to Command Asserted t4 nWRITE to Command t5 Command ...
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Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer ...
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PD<7:0> nSTROBE BUSY FIGURE 32 – PARALLEL PORT FIFO TIMING NAME t1 PDATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 PDATA Hold from nSTROBE Inactive (Note 1) t4 nSTROBE Active to BUSY Active t5 BUSY Inactive to ...
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PD<7:0> nACK nALF FIGURE 34 – ECP PARALLEL PORT REVERSE TIMING NAME t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted (Note 2) ...
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DATA IRRX n IRRX t1 Pulse Width at 1 15kba ud t1 Pul se Wid th at 57.6kba ud t1 Pul se Wid th at 38.4kba ud t1 Pul se Wid th at 19.2kba ...
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DAT IRT X n IRT X t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Widt 6kbaud t1 ...
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IRRX n IRRX IRRX IRRX t1 M odu lated Out put Bit T ime t2 Off Bit T ime t3 M odu lated Outp ut " On" ...
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DATA IRT X n IRT MIRTX MIRT odu lated Out put Bit Time t2 Off Bit Time t3 M odu lated Outp ut " On" ...
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PCI_CLK SER_IRQ NAME t1 SER_IRQ Setup Time to PCI_CLK Rising t2 SER_IRQ Hold Time to PCI_CLK Rising Data Start TXD1, 2 NAME t1 Serial Port Data Bit Time Note 1/Baud Rate. The Baud Rate is programmed through ...
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CLK KCLK/ 1 MCLK KDAT/ Start Bit Bit 0 MDAT FIGURE 43 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME t1 Time from DATA transition to falling edge of CLOCK (Receive) t2 Time from rising edge of ...
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FANx NAME DESCRIPTION t1 PWM Period (Note 1) t2 PWM High Time (Note 2) Note 1: The period is 1/f ,where f out f is +/- 2%. out Note 2: When Bit 0 of the FANx registers is 0, then ...
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PACKAGE OUTLINE Note: The following package information is preliminary. Contact SMSC for the latest information. FIGURE 48 – 128 PIN QFP PACKAGE OUTLINE MIN NOMINAL 0.05 A2 2.55 D 23.70 23.90 D/2 11.85 11.95 D1 19.90 ...