LPC47M192-NW Standard Microsystems (SMSC), LPC47M192-NW Datasheet

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LPC47M192-NW

Manufacturer Part Number
LPC47M192-NW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47M192-NW

Lead Free Status / RoHS Status
Compliant

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LPC47M192-NW
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LPC47M192-NW
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SMSC
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SMSC DS – LPC47M192
3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
LPC Interface
ACPI 1.0/2.0 Compliant
Fan Control
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-
Programmable Wake-up Event Interface
PC98, PC99, PC01 Compliant
Dual Game Port Interface
MPU-401 MIDI Support
General Purpose Input/Output Pins (37)
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
System Management Interrupt
2.88MB Super I/O Floppy Disk Controller
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Enhanced Digital Data Separator
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Keyboard Controller
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LPC Super I/O with Hardware Monitoring Block
Fan Speed Control Outputs (2)
Fan Tachometer Inputs (2)
Licensed CMOS 765B Floppy Disk
Controller
Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
Supports Two Floppy Drives
Configurable Open Drain/Push-Pull Output
Drivers
Supports Vertical Recording Format
16-Byte Data FIFO
100% IBM Compatibility
Detects All Overrun and Underrun
Conditions
Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
DMA Enable Logic
Data Rate and Drive Control Registers
480 Address, Up to 15 IRQ and Three
DMA Options
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbps Data Rates
Programmable Precompensation Modes
8042 Software Compatible
8 Bit Microcomputer
2k Bytes of Program ROM
256 Bytes of Data RAM
Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
Asynchronous Access to Two Data
Registers and One Status Register
Supports Interrupt and Polling Access
8 Bit Counter Timer
DATASHEET
FEATURES
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Serial Ports
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Infrared Port
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Multi-Mode Parallel Port with ChiProtect
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LPC Interface
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Hardware Monitor
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AMI Keyboard BIOS ROM
128 Pin QFP, 3.2mm footprint Package; green,
lead-free package also available
Port 92 Support
Fast Gate A20 and KRESET Outputs
Two Full Function Serial Ports
High Speed 16C550A Compatible UARTs
with Send/Receive 16-Byte FIFOs
Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
480 Address and 15 IRQ Options
Multiprotocol Infrared Interface
IrDA 1.0 Compliant
SHARP ASK IR
480 Addresses, Up to 15 IRQ
Standard Mode IBM PC/XT, PC/AT, and
PS/2 Compatible Bi-directional Parallel Port
Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284
Compliant)
IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
ChiProtect Circuitry for Protection
960 Address, Up to 15 IRQ and Three DMA
Options
Multiplexed Command, Address and Data
Bus
Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
PME Interface
Monitor Power supplies (+2.5V, +3.3V, +5V,
+12V, +1.8V, +1.5V, Vccp (processor
voltage), and VCC or HVSB)
Remote Thermal Diode Sensing for Two
External Temperature Measurements
Internal Ambient Temperature Measurement
Limit Comparison of all Monitored Values
System Management Bus (SMBus) Interface
THERM# Pin for out-of-limit Temperature or
Voltage Indication
RESET# Pin for generating 20msec Low
Reset Pulse
Configurable offset for internal or external
temperature channels.
LPC47M192
Rev. 03/30/05

Related parts for LPC47M192-NW

LPC47M192-NW Summary of contents

Page 1

... Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface - Asynchronous Access to Two Data Registers and One Status Register - Supports Interrupt and Polling Access - 8 Bit Counter Timer SMSC DS – LPC47M192 FEATURES - Port 92 Support - Fast Gate A20 and KRESET Outputs Serial Ports - Two Full Function Serial Ports ...

Page 2

... OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – LPC47M192 Page 2 DATASHEET Rev. 03/30/05 ...

Page 3

... Three DMA channels. The LPC47M192 does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. PART# LPC47M192-NC LPC47M192-NW SMSC DS – LPC47M192 ORDERING INFORMATION PACKAGE 128 Pin QFP 128 Pin QFP Green, Lead-Free ...

Page 4

... LOPPY ISK ONTROLLER 7.4.1 FDC Internal Registers ...........................................................................................................................31 7.4.2 STATUS REGISTER ENCODING ..........................................................................................................41 7.4.3 Instruction Set.........................................................................................................................................48 7.4.4 DATA TRANSFER COMMANDS............................................................................................................54 7.4.5 DIRECT SUPPORT FOR TWO FLOPPY DRIVES.................................................................................64 SMSC DS – LPC47M192 TABLE OF CONTENTS ........................................................................................................... .......................................................................... 20 ULLUP ESISTORS I ................................................................................................... 25 NPUT ............................................................................................................. 25 (PME/SCI)....................................................................................... 26 (LPC) ............................................................................................... 27 .............................................................................................................. 31 Page 4 DATASHEET Rev. 03/30/05 ...

Page 5

... Input Monitoring ........................................................................................................................................... 132 7.18.3.2 Resetting the Hardware Monitoring Block.................................................................................................... 132 7.18.3.3 Reset Out Pin ................................................................................................................................................ 133 7.18.3.4 Monitoring Modes......................................................................................................................................... 133 7.18.3.5 Interrupt Status Registers .............................................................................................................................. 134 7.18.3.6 Low Power Modes ........................................................................................................................................ 134 SMSC DS – LPC47M192 D .............................................................................. 105 ESCRIPTION I ........................................................................................... 129 NTERFACE Page 5 DATASHEET Rev. 03/30/05 ...

Page 6

... UPER LOCK 16.1.1 Board Test Mode...............................................................................................................................223 16 ARDWARE ONITORING 16.2.1 Board Test Mode...............................................................................................................................225 16.2.2 XNOR-Chain Test Mode ...................................................................................................................225 17 APPENDIX D - REFERENCE DOCUMENTS................................................................................. 227 18 LPC47M192 REVISIONS................................................................................................................ 228 SMSC DS – LPC47M192 ........................................................................................................... 167 /C R ONFIGURATION EGISTERS / 30-0 ONTROL EGISTERS EVICE ONFIGURATION EGISTERS ...

Page 7

... Table 58 - SMBus Read Byte Protocol.......................................................................................................................131 Table 59 - SMBus Send Byte Protocol.......................................................................................................................131 Table 60 - SMBus Receive Byte Protocol ..................................................................................................................131 Table 61 - Modified SMBus Receive Byte Protocol Response to ARA ......................................................................132 Table 62 - Runtime Register Block Summary ............................................................................................................139 SMSC DS – LPC47M192 TABLES Page 7 DATASHEET Rev. 03/30/05 ...

Page 8

... Table 63 - Runtime Register Block Description..........................................................................................................142 Table 64 – LPC47M192 Configuration Registers Summary.....................................................................................168 Table 65 - Chip Level Registers .................................................................................................................................170 Table 66 - Logical Device Registers...........................................................................................................................173 Table 67 – I/O Base Address Configuration Register Description............................................................................175 Table 68 - Interrupt Select Configuration Register Description ..................................................................................176 Table 69 – DMA Channel Select Configuration Register Description.......................................................................177 Table 70 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] ...

Page 9

... FIGURE 1 – LPC47M192 BLOCK DIAGRAM ............................................................................................................22 FIGURE 2 - MPU-401 MIDI INTERFACE ....................................................................................................................78 FIGURE 3 - MPU-401 INTERRUPT.............................................................................................................................81 FIGURE 4 - MIDI DATA BYTE EXAMPLE ...................................................................................................................82 FIGURE 5 - KEYBOARD LATCH...............................................................................................................................111 FIGURE 6 - MOUSE LATCH......................................................................................................................................111 FIGURE 7 - GPIO FUNCTION ILLUSTRATION ........................................................................................................116 FIGURE 8 − FAN TACHOMETER INPUT AND CLOCK SOURCE............................................................................123 FIGURE 9 − CONCEPTUAL BLOCK DIAGRAM OF FAN MONITORING LOGIC .....................................................124 FIGURE 10 − ...

Page 10

... GP43/DDRC 29 PCI_CLK 30 SER_IRQ 31 VSS 32 GP10 /J1B1 33 GP11 /J1B2 34 GP12 /J2B1 35 GP13 /J2B2 36 GP14 /J1X 37 GP15 /J1Y 38 GP16 /J2X SMSC DS – LPC47M192 LPC47M192 128 PIN QFP Page 10 DATASHEET 102 HVCC 101 HVSS 100 GP57/nDTR2 99 GP56/nCTS2 98 GP55/nRTS2 97 GP54/nDSR2 96 GP53/TXD2 (IRTX) 95 GP52/RXD2 (IRRX) 94 GP51/nDCD2 ...

Page 11

... LDRQ PCI_RESET LPCPD GP43/DDRC 60 29 PCI_CLK 61 30 SER_IRQ 62 31 VSS 63 32 GP10 /J1B1 64 SMSC DS – LPC47M192 NAME PIN # GP11 /J1B2 65 VCC GP12 /J2B1 66 nINIT GP13 /J2B2 67 nSLCTIN GP14 /J1X 68 PD0 GP15 /J1Y 69 PD1 GP16 /J2X 70 PD2 GP17 /J2Y 71 PD3 AVSS ...

Page 12

... PCI_RESET# Active low input used as LPC Interface Reset. 27 LPCPD# Active low input Power Down signal indicates that the LPC47M192 should prepare for power to be shut-off on the LPC interface. 29 PCI_CLK PCI clock input. 30 SER_IRQ Serial IRQ pin used with the PCI_CLK pin to transfer LPC47M192 interrupts to the host ...

Page 13

... GP41/ General Purpose I/O DRVDEN1 Drive Density Select 1 Output. Indicates the drive and media selected. Both functions can be configured as Open- Drain Output. SMSC DS – LPC47M192 DESCRIPTION O12 Can be This high current O12 O12 A logic “1” on this pin This active low high ...

Page 14

... MSR read will set MSR bit bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. SMSC DS – LPC47M192 DESCRIPTION SERIAL PORT 1 INTERFACE (8) The hardware reset will Handshake output signal nDTR is forced ...

Page 15

... GP57/ General Purpose I/O. configured as an Open-Drain Output. Data Terminal Ready Output. See nDTR1 nDTR2 pin description above. SMSC DS – LPC47M192 DESCRIPTION The CPU can monitor the A nDCD The CPU can INFRARED INTERFACE (2) GPIO can be GPIO can be SERIAL PORT 2 INTERFACE (8) ...

Page 16

... Bit 6 of the Printer Status Register reads the nACK input. Parallel Port description for use of this pin in ECP and EPP mode. SMSC DS – LPC47M192 DESCRIPTION GPIO can be GPIO can be GPIO can be ...

Page 17

... General Purpose I/O. configured as an Open-Drain Output Joystick 1 Y-Axis I/O J1Y 38 GP16/ General Purpose I/O. configured as an Open-Drain Output Joystick 2 X-Axis I/O J2X SMSC DS – LPC47M192 DESCRIPTION Refer to Parallel Port Refer to KEYBOARD/MOUSE INTERFACE (6) GPIO can be GPIO can be GAME PORT (8) GPIO can be GPIO can be ...

Page 18

... J2Y 17 GP42/ General Purpose I/O. nIO_PME Power Management Event Output. active low Power Management Event signal allows the LPC47M192 to request wakeup. Both functions can be configured as an Open-Drain Output. 28 GP43/ General Purpose I/O. configured as an Open-Drain Output. Device Disable Reg. Control Input ...

Page 19

... Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’ if the clock is not connected. SMSC DS – LPC47M192 DESCRIPTION HARDWARE MONITORING BLOCK (28) ...

Page 20

... Pins That Require External Pullup Resistors 4.2.1 SUPER I/O PINS The following pins require external pullup resistors: KDAT KCLK MDAT MCLK GP36/KBDRST if KBDRST function is used GP37/A20M if A20M function is used GP20/P17 If P17 function is used as an Open Drain Output SMSC DS – LPC47M192 Page 20 DATASHEET Rev. 03/30/05 ...

Page 21

... The following pins require external pullup resistors to 3.3V only: SCLK SDA A0/RESET#/THERM#/XNOR_OUT if the RESET# or THERM# function is used. This limits the SMBus address to 0101101 (unless external circuitry is provided). See section 7.18.2 SMBus Interface. VID0-VID3 12V_IN/VID4 if VID4 function is used. SMSC DS – LPC47M192 Page 21 DATASHEET Rev. 03/30/05 ...

Page 22

... WDATA WCLOCK DIGITAL DATA SMC PROPRIETARY SEPARATOR 82077 COMPATIBLE WITH WRITE VERTICAL PRECOM- FLOPPYDISK PENSATION CONTROLLER CORE RCLOCK RDATA FIGURE 1 – LPC47M192 BLOCK DIAGRAM Page 22 DATASHEET LEDs PD[7,0] Multi-Mode Busy, Slct, PE, Parallel Port ERROR, ACK with ChiProtect TM / STROBE, INIT, SLCTIN, FDC MUX ...

Page 23

... The LPC47M192 has four power planes: VCC, HVCC, VREF, and VTR. 6.1 VCC/HVCC Power The LPC47M192 is a 3.3 Volt part. The VCC/HVCC supply is 3.3 Volts (nominal). VCC is supply for Super I/O Block, and HVCC is supply for the Hardware Monitoring Block. See the “Operational Description” Section and the “ ...

Page 24

... Pins for PME Wakeup: - GP42/nIO_PME (output, buffer powered by VTR) - nRI1 (input) - GP50/nRI2 (input) - KDAT (input) - MDAT (input) - GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61) – all input-only except GP53, GP60, GP61. See below. SMSC DS – LPC47M192 Page 24 DATASHEET Rev. 03/30/05 ...

Page 25

... INDICATION OF 32KHZ CLOCK There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M192. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR. ...

Page 26

... Monitoring Block Specifications” section of the “Operation Description” section. 6.7 Power Management Events (PME/SCI) The LPC47M192 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “ ...

Page 27

... FUNCTIONAL DESCRIPTION The following sections describe the functional blocks located in the LPC47M192 (see FIGURE 1). All the functional blocks are dedicated to the Super I/O portion of the chip, except for the Hardware Monitoring block. The Hardware Monitoring block is maintained separately from the Super I/O components and is defined in section 7.18 − ...

Page 28

... LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal used by the LPC47M192 to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M192 monitors the bus to determine whether the cycle is intended for it ...

Page 29

... DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M192. DMA write cycles involve the transfer of data from the LPC47M192 to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M192 are bytes. ...

Page 30

... The LPC47M192 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M192, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M192. If the host was writing data to the LPC47M192, the data had already been transferred. ...

Page 31

... IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. LPC47M192 supports two floppy drive directly (see “Direct Support for Two Floppy Drives” subsection). The FDC is compatible to the 82077AA using SMSC’s proprietary floppy disk controller core. ...

Page 32

... This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET 1 COND. SMSC DS – LPC47M192 DRQ STEP TRK0 nHDSEL F/F ...

Page 33

... Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. SMSC DS – LPC47M192 nDS1 ...

Page 34

... This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active. DRIVE 0 1 Table 3 – Internal 2 Drive Decode – Normal DIGITAL OUTPUT REGISTER Bit 5 Bit 4 Bit1 SMSC DS – LPC47M192 MOT MOT DMAEN EN1 EN0 DOR VALUE 1CH 2DH DRIVE SELECT OUTPUTS (ACTIVE LOW) Bit 0 nDS1 ...

Page 35

... X BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M192. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M192. TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization ...

Page 36

... The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. SMSC DS – LPC47M192 ...

Page 37

... Drive Rate Table (Recommended 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins. DT1 DT0 SMSC DS – LPC47M192 Table 8 – Data Rates DATA RATE DATA RATE SEL1 SEL0 MFM 1Meg --- ...

Page 38

... An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. SMSC DS – LPC47M192 5 4 ...

Page 39

... BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. SMSC DS – LPC47M192 Table 11 – FIFO Service Delay MAXIMUM DELAY TO SERVICING AT 2 Mbps DATA RATE ...

Page 40

... BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT 2 – 7 RESERVED Should be set to a logical “0” SMSC DS – LPC47M192 unaffected by a software reset, and are set to 250 Kbps after a 6 ...

Page 41

... BIT NO. SYMBOL 7 1,0 DS1,0 BIT NO. SYMBOL SMSC DS – LPC47M192 N/A N/A N/A N/A Table 12 – Status Register 0 NAME Interrupt Code 00 - Normal termination of command. command was properly executed and completed without error Abnormal termination of command. execution was started, but was not successfully completed ...

Page 42

... 1,0 DS1,0 SMSC DS – LPC47M192 NAME Overrun/ Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data Underrun overrun or underrun. Unused. This bit is always "0". No Data Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector ...

Page 43

... The DMA and interrupt functions are always enabled, and DENSEL is active low. Model 30 mode This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low. SMSC DS – LPC47M192 Page 43 DATASHEET Rev. 03/30/05 ...

Page 44

... DMA controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has <threshold> bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more data is required. SMSC DS – LPC47M192 Page 44 DATASHEET ...

Page 45

... Size EC Enable Count EFIFO Enable FIFO EIS Enable Implied Seek EOT End of Track SMSC DS – LPC47M192 DESCRIPTION The currently selected address 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular Perpendicular Mode Command. A “1” indicates a perpendicular drive ...

Page 46

... Polling Disable PRETRK Precompensation Start Track Number R Sector Address SMSC DS – LPC47M192 DESCRIPTION Alters Gap 2 length when using Perpendicular Mode. The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head (disk side encoded in the sector ID field. ...

Page 47

... ST2 Status 2 ST3 Status 3 WGATE Write Gate SMSC DS – LPC47M192 DESCRIPTION Relative cylinder offset from present cylinder as used by the Relative Seek command. The number of sectors per track to be initialized by the Format command. The number of sectors per track to be verified during a Verify command when EC is set. ...

Page 48

... INSTRUCTION SET PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – LPC47M192 Table 17 – Instruction Set READ DATA DATA BUS HDS DS1 DS0 EOT GPL DTL ST0 ST1 ST2 READ DELETED DATA DATA BUS ...

Page 49

... PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – LPC47M192 WRITE DATA DATA BUS HDS DS1 DS0 EOT GPL DTL ST0 ST1 ST2 WRITE DELETED DATA DATA BUS HDS DS1 EOT GPL DTL ST0 ...

Page 50

... PHASE R/W D7 Command Execution Result PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – LPC47M192 READ A TRACK DATA BUS MFM HDS DS1 EOT GPL DTL ST0 ST1 ST2 VERIFY DATA BUS HDS DS1 EOT GPL DTL/SC ST0 ST1 ST2 Page 50 DATASHEET ...

Page 51

... Command W 0 Result R 1 PHASE R/W D7 Command Execution for Each Sector Repeat Result PHASE R/W D7 Command Execution PHASE R/W D7 Command W 0 Result R R SMSC DS – LPC47M192 VERSION DATA BUS FORMAT A TRACK DATA BUS MFM HDS DS1 N SC GPL ST0 ST1 ST2 ...

Page 52

... W W PHASE R/W D7 Command Result R PHASE R/W D7 Command Execution PHASE R/W D7 Command Execution W PHASE R/W D7 Command PHASE R/W D7 Command W Execution Result SMSC DS – LPC47M192 SPECIFY DATA BUS SRT HUT HLT SENSE DRIVE STATUS DATA BUS HDS DS1 ST3 SEEK DATA BUS ...

Page 53

... SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins the user’s responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). SMSC DS – LPC47M192 DUMPREG DATA BUS D6 D5 ...

Page 54

... Status Register 1 to “1”, sets the DD bit in Status Register 2 to “1” if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 20 describes the effect of the SK bit on the Read Data command SMSC DS – LPC47M192 Table 18 – Sector Sizes ...

Page 55

... This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data SMSC DS – LPC47M192 Table 19 – Effects of MT and N Bits ...

Page 56

... This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. SMSC DS – LPC47M192 Table 22 – Result Phase Table ID INFORMATION AT RESULT PHASE ...

Page 57

... This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command. SMSC DS – LPC47M192 SC/EOT VALUE TERMINATION RESULT Success Termination ...

Page 58

... ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex. SMSC DS – LPC47M192 FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT SYNC IDAM C ...

Page 59

... The H bit (Head Address) in ST0 will always return to a “0”. When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command highly recommended that the user service all pending interrupts through the Sense Interrupt Status command. SMSC DS – LPC47M192 Page 59 DATASHEET ...

Page 60

... Table 26. The values are the same for MFM and FM. DMA operation is selected by the ND bit. When ND is “0”, the DMA mode is selected. This part does not support non-DMA mode. In DMA mode, data transfers are signaled by the DMA request cycles. SMSC DS – LPC47M192 Table 25 – Interrupt Identification SE ...

Page 61

... The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. SMSC DS – LPC47M192 Table 26 – Drive Control Delays (ms) HUT 500K 300K 250K ...

Page 62

... But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. SMSC DS – LPC47M192 DIR ACTION 0 ...

Page 63

... All “hardware” RESET from the PCI_RESET# pin will set the LOCK bit to logic “0” and return the EFIFO, FIFOTHR, and PRETRK to their default values. command. This byte reflects the value of the LOCK bit set by the command byte. SMSC DS – LPC47M192 Table 27 – Effects of WGATE and GAP Bits LENGTH OF ...

Page 64

... DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The LPC47M192 was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems ...

Page 65

... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M192. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below ...

Page 66

... By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1. Receiver Line Status (highest priority) 2. Received Data Ready 3. Transmitter Holding Register Empty 4. MODEM Status (lowest priority) SMSC DS – LPC47M192 Page 66 DATASHEET Rev. 03/30/05 ...

Page 67

... These two bits are set when the FIFO CONTROL Register bit 0 equals 1. FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT 3 BIT 2 BIT 1 BIT SMSC DS – LPC47M192 RCVR FIFO Bit 7 Bit 6 Trigger Level (BYTES Table 29 – Interrupt Control Table INTERRUPT SET AND RESET FUNCTIONS PRIORIT INTERRUPT Y LEVEL TYPE ...

Page 68

... SMSC DS – LPC47M192 INTERRUPT SET AND RESET FUNCTIONS ...

Page 69

... Data that is transmitted is immediately received. This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also SMSC DS – LPC47M192 Page 69 DATASHEET ...

Page 70

... Transmitter Shift Register (TSR) are both empty reset to logic “0” whenever either the THR or TSR contains a data character. Bit read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty, SMSC DS – LPC47M192 Page 70 DATASHEET Rev ...

Page 71

... This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to OUT2 in the MCR. SMSC DS – LPC47M192 Page 71 DATASHEET Rev. 03/30/05 ...

Page 72

... The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate enabled. SMSC DS – LPC47M192 Page 72 DATASHEET Rev. 03/30/05 ...

Page 73

... The High Speed bit is located in the Device Configuration Space. REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. SMSC DS – LPC47M192 Table 30 - Baud Rates PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 2304 1536 1047 857 768 ...

Page 74

... Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. SMSC DS – LPC47M192 RESET CONTROL RESET ...

Page 75

... Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21). SMSC DS – LPC47M192 BIT 4 BIT 5 ...

Page 76

... Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). SMSC DS – LPC47M192 Page 76 DATASHEET Rev. 03/30/05 ...

Page 77

... The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. The following figure shows the block diagram of the IR components in the LPC47M192: Host Interface IR Transmit Pins The following description pertains to the TXD2/IRTX and IRTX2 pins of the LPC47M192 ...

Page 78

... The IRTX2 pin is not affected by the TXD2_MODE bit. 7.7 MPU-401 MIDI UART 7.7.1 OVERVIEW Serial Port 3 is used exclusively in the LPC47M192 as an MPU-401-compatible MIDI Interface. The LPC47M192 MPU-401 hardware includes a Host Interface, an MPU-401 command controller, configuration registers, and a compatible UART (FIGURE 2). ...

Page 79

... The Sound Blaster 16 MPU-401 UART mode MIDI interface requires two consecutive I/O addresses with possible base I/O addresses of 300h and 330h. The default is 330h. The LPC47M192 MPU-401 I/O base address is programmable on even-byte boundaries throughout the entire I/O address range (see Section “Activate and I/O Base address” ...

Page 80

... The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is write- only (Table 38). See Section “MPU-401 Command controller” below TYPE W W NAME SMSC DS – LPC47M192 DESCRIPTION MIDI Read/Command Acknowledge data is available to the host. MIDI Read/Command Acknowledge data is NOT available to the host. Table 37 - MIDI TRANSMIT BUSY STATUS BIT DESCRIPTION The MPU-401 interface is ready to accept a data/command byte from the host ...

Page 81

... When the MPU-401 is reset, receive data from the MIDI_IN port as well as data written by the host to the MIDI Data port is ignored. The MPU-401 MIDI Interface is reset following the RESET command or POR. SMSC DS – LPC47M192 MIDI RX DATA BYTE N+1 FIGURE 3 - MPU-401 INTERRUPT Page 81 ...

Page 82

... MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32µs. 7.7.7 MPU-401 CONFIGURATION REGISTERS The LPC47M192 configuration registers are in Logical Device B (see “Configuration” section). The configuration registers contain the MPU-401 Activate, Base Address and Interrupt select. The defaults for the Base Address and Interrupt Select configuration registers match the MPU-401 factory defaults. SMSC DS – ...

Page 83

... See Section “Host Interface”. 7.8 PARALLEL PORT The LPC47M192 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi- directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes ...

Page 84

... The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. BIT PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. SMSC DS – LPC47M192 STANDARD EPP (User Defined) PE ...

Page 85

... RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - SMSC DS – LPC47M192 Page 85 DATASHEET ...

Page 86

... Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. 5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. SMSC DS – LPC47M192 Page 86 DATASHEET Rev. 03/30/05 ...

Page 87

... The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE. 2. The host initiates an I/O write cycle to the selected EPP register. 3. The chip places address or data on PData bus. 4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. SMSC DS – LPC47M192 Page 87 DATASHEET Rev. 03/30/05 ...

Page 88

... RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability. SMSC DS – LPC47M192 Table 40 - EPP Pin Descriptions TYPE ...

Page 89

... The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is SMSC DS – LPC47M192 ...

Page 90

... R cnfgB +401h R/W ecr +402h R/W SMSC DS – LPC47M192 Table 41 – ECP Pin Descriptions DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse ...

Page 91

... The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. SMSC DS – LPC47M192 Table 43 - Mode Descriptions DESCRIPTION* Page 91 DATASHEET Rev ...

Page 92

... ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. SMSC DS – LPC47M192 Page 92 DATASHEET enable interrupt requests from the Rev ...

Page 93

... BITS [2:0] Parallel Port DMA (read-only) to Table 44C ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. SMSC DS – LPC47M192 Page 93 DATASHEET Rev. 03/30/05 ...

Page 94

... All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). SMSC DS – LPC47M192 Table 44a - Extended Control Register MODE Page 94 DATASHEET ...

Page 95

... Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the SMSC DS – LPC47M192 BITS 5:3 DMA ...

Page 96

... This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. An interrupt is generated when: 1) For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received. 2) For Programmed I/O: SMSC DS – LPC47M192 D7 D[6:0] 0 Run-Length Count (0-127) ...

Page 97

... To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. SMSC DS – LPC47M192 Page 97 DATASHEET Rev. 03/30/05 ...

Page 98

... If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. SMSC DS – LPC47M192 = (16-<threshold>) free bytes in FIFO Page 98 ...

Page 99

... The pins of the LPC47M192 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part’ ...

Page 100

... Auto Power Management is enabled by CR23-B6. When set, this bit allows the following auto power management operations 1. The transmitter enters auto powerdown when the transmit buffer and shift register are empty 2. The receiver enters powerdown when the following conditions are all met: SMSC DS – LPC47M192 STATE IN AUTO POWERDOWN STATE IN AUTO POWERDOWN INPUT PINS Input Input ...

Page 101

... SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. SMSC DS – LPC47M192 Page 101 DATASHEET Rev. 03/30/05 ...

Page 102

... Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. Any SER_IRQ Device (i.e., The LPC47M192) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle SMSC DS – ...

Page 103

... Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode. SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47M192 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...

Page 104

... SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes. SMSC DS – LPC47M192 Page 104 DATASHEET Rev. 03/30/05 ...

Page 105

... Keyboard Controller Description The LPC47M192 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard manage- ment in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the LPC47M192 enhancements to the 8042. For general information about the 8042, refer to the “ ...

Page 106

... This bit read only register. Refer to the description of the Status Register for more information. CPU-to-Host Communication The LPC47M192 CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 50. ...

Page 107

... If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the LPC47M192 CPU has read the DBB register. If “EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. ...

Page 108

... Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M192 CPU. UD Writable by LPC47M192 CPU. These bits are user-definable. C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data command). During a host data/command write operation, this bit is set to “ ...

Page 109

... DEFAULT RESET CONDITIONS The LPC47M192 has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 52 for the effect of each type of reset on the internal registers. DESCRIPTION Host I/F Data Reg Host I/F Status Reg GATEA20 AND KEYBOARD RESET The LPC47M192 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET ...

Page 110

... CPU low, if A20GATE from the keyboard controller is also low. Writing bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low. SMSC DS – LPC47M192 nGATEA20 8042 ...

Page 111

... Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. 8042 8042 SMSC DS – LPC47M192 KLATCH Bit VCC D Q KINT CLR RD 60 FIGURE 5 - KEYBOARD LATCH MLATCH Bit VCC D Q MINT CLR RD 60 FIGURE 6 - MOUSE LATCH ...

Page 112

... PME events. The LPC47M192 has “isolation” bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. These bits may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state ...

Page 113

... GENERAL PURPOSE I/O The LPC47M192 provides a set of flexible Input/Output control functions to the system designer through the 37 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME. ...

Page 114

... Joystick 1 X-Axis 37 GPIO Joystick 1 Y-Axis 38 GPIO Joystick 2 X-Axis 39 GPIO Joystick 2 Y-Axis 41 GPIO 42 GPIO 43 GPIO N/A Reserved 45 GPIO (System Option) 46 GPIO MIDI_IN 47 GPIO MIDI_OUT SMSC DS – LPC47M192 REG PCI VCC VTR OFFS REG RESET POR POR ET (hex GP43 - - In 3F GP50 - - In 40 GP51 - ...

Page 115

... GP15, GP16 and GP17), these pins become open drain, non-inverted outputs. The basic GPIO configuration options are summarized in Table 54. SELECTED DIRECTION FUNCTION GPIO SMSC DS – LPC47M192 ALT. ALT. FUNC. 2 FUNC. 3 EETI EETI ...

Page 116

... WRITE NO EFFECT The LPC47M192 provides 31 GPIOs that can directly generate a PME. See the table in the next section. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS 2 register. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN 2 register and the PME_EN bit in the PME_EN register is set, a PME will be generated ...

Page 117

... Logical Device A. The PME status bits for the GPIOs are cleared on a write of ‘1’. In addition, the LPC47M192 provides 19 GPIOs that can directly generate an SMI. See the table in the next section. 7.12.5 GPIO PME AND SMI FUNCTIONALITY The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable ...

Page 118

... LED FUNCTIONALITY The LPC47M192 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A. ...

Page 119

... ACPI system. A power management event is indicated to the chipset via the assertion of the nIO_PME signal. In the LPC47M192, the nIO_PME is asserted by active transitions on the ring indicator inputs nRI1 and nRI2, valid NEC infrared remote control frames, active keyboard-data edges, active mouse-data edges, programmable edges on GPIO pins and fan tachometer event ...

Page 120

... See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals to generate a PME. In the LPC47M192 the nIO_PME pin can be programmed open drain, active low, driver. The LPC47M192 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low; i.e., the nIO_PME signal is capable of being driven high externally by another active device or pullup even when the LPC47M192 VCC is grounded, providing VTR power is active ...

Page 121

... FAN SPEED CONTROL AND MONITORING The LPC47M192 can control the speed of two separate fans as well as monitor them if they are equipped with fan tachometer outputs. The following sections will clarify how this chip controls the speed of a fan and its’ monitoring capabilities ...

Page 122

... Clock Multiplier bits in the Fan Control register to determine the fan speed F Duty Cycle Control for Fan x, Bits D6 – D1 The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47M192 has ≈ 1.56% duty cycle resolution. When DCC = “000000” (min. value almost always high ...

Page 123

... Fan Tachometer register has been updated if the fan suddenly seizes, a second PME is generated when the counter reaches 0xFF and the Fan Tachometer register is latched again. The Fan Tachometer register will remain at this value until another Fan Tachometer input pulse is received. A representation of the logic for the fan tachometer implementation is shown below. SMSC DS – LPC47M192 ...

Page 124

... Term 1 in the equation above is ½ of the value determined by multiplying the clock source of 32.768kHz by 60sec/min and dividing by the product of the revolutions per minute times the divisor. The factor of ½ in Term 1 corresponds to two pulses per revolution. The default divisor, located in the Fan Control Register, is two. This results SMSC DS – LPC47M192 Preload Divider ...

Page 125

... The configuration register for the device disable register is defined in the “Runtime Registers” section. 7.17 GAME PORT LOGIC The LPC47M192 implements logic to support a dual game port. This logic includes the following for each game port: two 555 timers, two game port RC constant inputs (x-axis and y-axis), two game port button inputs and game port interface logic ...

Page 126

... The figure below illustrates the implementation of the game port logic in the LPC47M192. Internal To LPC47M192 JOYW JOYR Game Port Register Game software will write a byte to the game port to reset it, and then poll (read) the port until the x and y-axis RC time constant pins (TIMA,B) time out (return to zero). The elapsed time indicates the resistance value of the potentiometer and in turn, the position of the joystick ...

Page 127

... Note: Register 0x60 is the high byte; 0x61 is the low byte. For example, to set the primary base address to 1234h, write 12h into 0x60, and 34h into 0x61. When the activate bit in Logical Device 9 is cleared, it prevents the base I/O address for the game port from being decoded. SMSC DS – LPC47M192 t1 Page 127 DATASHEET ...

Page 128

... VREF PIN The LPC47M192 has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply used for the game port. The reference voltage is used in the game port logic so that the joystick trigger voltage is 2/3 VREF where VREF is either ...

Page 129

... The host processor communicates with the Hardware Monitor Block through a series of read/write registers via the SMBus interface. SMBus is a serial communication protocol between a computer host and its peripheral devices. The SMBus protocol includes a physical layer based on the I SMSC DS – LPC47M192 TYPE System Management Bus bi-directional Data. ...

Page 130

... Read Byte The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in Table 2 is performed correctly. Only one byte is transferred at time for a Read Byte protocol. SMSC DS – LPC47M192 Table 57 - SMBus Write Byte Protocol REG. ...

Page 131

... SMBus Slave Interface will return to the idle state. 7.18.2.1.4 General Call Address Response The Hardware Monitor Block will not respond to a general call address of 0000_000. SMSC DS – LPC47M192 Table 58 - SMBus Read Byte Protocol REG. SLAVE ACK ...

Page 132

... Register Summary subsection. The default state of Value or Limit Registers are not shown because these registers have indeterminate power on values. Usually the first action after power write limits into the Limit Registers. SMSC DS – LPC47M192 Min = 25ms. TIME-OUT ...

Page 133

... The continuous monitoring function is started by doing a write to the Configuration Register, setting the Start bit (Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown below (corresponding to locations in the Value RAM). Sampling of all values occurs in 542.336 ms (or 67.792ms - see above). SMSC DS – LPC47M192 Page 133 DATASHEET ...

Page 134

... The Hardware Monitor Block can be placed in a low-power mode by writing a ‘0’ to the Configuration Register (0x40). The low power mode that is entered is either sleep mode or shutdown mode as selected using bit 0 of the Special Function Register (4F). These modes do not reset any of the registers of the Hardware Monitor Block. SMSC DS – LPC47M192 REGISTER 1 ...

Page 135

... Dx-). The value is stored in the Remote Diode Temperature Reading 1 register (0x26) for D0+ and D0- pins. The value is stored in the Remote Diode Temperature Reading 2 register (0x52) for D1+ and D1- pins. If this value is out-of-limit (or equal to) the programmed limits (for D0+ and D0- pins, or D1+ and D1- pins) in Remote SMSC DS – LPC47M192 + ...

Page 136

... Error status bit is set in the Interrupt Status Register 1. There are Remote Diode Fault status 1 and 2 bits in the Status Register 2 (0x42). The LPC47M192 automatically sets the associated diode fault bit to 1 when there is an open circuit fault on the Remote x+ or Remote x- thermal diode input pins ...

Page 137

... The THERM# pin may only become active while the monitor block is operational. Implementation Note: In designs using the Hardware Monitor Block of the LPC47M192, all the remote thermal diode inputs must be properly terminated, even if one or both of the remote temperature sensor channels will not be used to actively monitor temperatures ...

Page 138

... FIGURE 11 − USING A DIODE AS A REMOTE TEMPERATURE SENSING ELEMENT 4. Place 0.1uF (ceramic) bypass and 20uF (electrolytic or tantalum) capacitors in parallel between the power supply (HVCC) and ground. They should be kept as close to the hardware monitoring block as possible. SMSC DS – LPC47M192 Dx+ External Temperature 2.2nF ...

Page 139

... RUNTIME REGISTERS The following registers are runtime registers in the LPC47M192. They are located at the address programmed in the Base I/O Address in Logical Device A (also referred to as the Runtime Register) at the offset shown. These registers are powered by VTR. Table 62 - Runtime Register Block Summary ...

Page 140

... R/W - Note R/W - Note SMSC DS – LPC47M192 SOFT VCC POR VTR POR RESET - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - - - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - 0x00 0x01 - 0x00 0x01 - - 0x05 - 0x04 0x04 - - 0x01 - - ...

Page 141

... VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be set on a VCC POR. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0). SMSC DS – LPC47M192 SOFT VCC POR ...

Page 142

... SMSC DS – LPC47M192 DESCRIPTION (hex) 00 Bit[0] PME_Status = 0 (default) (R/ Set when LPC47M192 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a “1” to PME_Status will clear it and cause the LPC47M192 to stop asserting nIO_PME, in enabled. Writing a “ ...

Page 143

... REG OFFSET NAME PME_STS2 Default = 0x00 on VTR POR PME_STS3 Default = 0x00 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 05 PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of the individual source (R/W) enables or the PME_En bit. ...

Page 144

... PME_STS4 Default = 0x00 on VTR POR (Note 6) PME_STS5 Default = 0x00 on VTR POR (Note 6) N/A SMSC DS – LPC47M192 DESCRIPTION (hex) 07 PME Wake Status Register 4 This register indicates the state of the individual PME wake sources, independent of the individual source (R/W) enables or the PME_En bit. ...

Page 145

... The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. 0B PME Wake Enable Register 2 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. (R/W) When the PME Wake Enable register bit for a wake source is active (“ ...

Page 146

... The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. 0D PME Wake Enable Register 4 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. (R/W) When the PME Wake Enable register bit for a wake source is active (“ ...

Page 147

... SMSC DS – LPC47M192 DESCRIPTION (hex) 0E PME Wake Enable Register 5 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. (R/W) When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...

Page 148

... SMI_STS5 Default = 0x00 on VTR POR N/A SMI_EN1 Default = 0x00 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 12 SMI Status Register 3 This register is used to read the status of the SMI inputs. (R/W) The following bits are cleared on a write of ‘1’. Bit[0] GP20 ...

Page 149

... Default = 0x00 on VTR POR SMI_EN3 Default = 0x00 on VTR POR SMI_EN4 Default = 0x00 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 17 SMI Enable Register 2 This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI (R/W) output onto the nIO_SMI GPI/O pin, the serial IRQ stream or into the PME Logic ...

Page 150

... REG OFFSET NAME SMI_EN5 Default = 0x00 on VTR POR N/A MSC_STS Default = 0x00 on VTR POR N/A SMSC DS – LPC47M192 DESCRIPTION (hex) 1A SMI Enable Register 5 This register is used to enable the different interrupt sources onto the group nSMI output. (R/W) 1=Enable 0=Disable Bit[0] GP54 ...

Page 151

... Reset and VTR POR Floppy Data Rate Select Shadow UART1 FIFO Control Shadow UART2 FIFO Control Shadow SMSC DS – LPC47M192 DESCRIPTION (hex) 1E Force Disk Change Bit[0] Force Disk Change for FDC0 (R/W) 0=Inactive 1=Active Bit[1] Force Disk Change for FDC1 0=Inactive ...

Page 152

... When register =01 AND GP43 pin = 1 GP10 Default = 0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex “0” (enabled), bits[7:3] have no effect on the devices; devices are controlled by their respective activate bits. If “1” (disabled), bits[7:3] override the activate bits in the configuration registers for each logical block. ...

Page 153

... GP13 Default = 0x01 on VTR POR GP14 Default = 0x01 on VTR POR GP15 Default = 0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 24 General Purpose I/0 bit 1.1 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1= J1B2 (Joystick 1, Button 2) ...

Page 154

... GP17 Default = 0x01 on VTR POR GP20 Default = 0x01 on VTR POR GP21 Default =0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 29 General Purpose I/0 bit 1.6 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1= J2X (Joystick 2, X-Axis RC Constant) ...

Page 155

... GP24 Default = 0x01 on VTR POR GP25 Default = 0x01 on VTR POR GP26 Default = 0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 2D General Purpose I/0 bit 2.2 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select 11= nMTR1 – Floppy Motor Select 1 (Note 4) ...

Page 156

... Default = 0x01 on VTR POR GP32 Default = 0x01 on VTR POR Default = 0x00 on VCC POR and PCI Reset (Note 3) SMSC DS – LPC47M192 DESCRIPTION (hex) 32 General Purpose I/0 bit 2.7 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=nIO_SMI (Note 5) ...

Page 157

... VTR POR, VCC POR and PCI Reset (Note 3) GP36 Default = 0x01 on VTR POR GP37 Default = 0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 36 General Purpose I/0 bit 3.3 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select ...

Page 158

... NAME GP40 Default =0x01 on VTR POR GP41 Default =0x01 on VTR POR GP42 Default =0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 3B General Purpose I/0 bit 4.0 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=DRVDEN0 (Note 4) ...

Page 159

... VCC POR, VTR POR and PCI Reset GP50 Default = 0x01 on VTR POR GP51 Default = 0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 3E General Purpose I/0 bit 4.3 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select 11=Either Edge Triggered Interrupt Input 3 (Note 1) 10=Reserved 01=Device Disable Register Control ...

Page 160

... VTR POR, VCC POR and PCI Reset (Note 3) GP54 Default = 0x01 on VTR POR GP55 Default = 0x01 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 41 General Purpose I/0 bit 5.2 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select ...

Page 161

... GP57 Default = 0x01 on VTR POR GP60 Default = 0x01 on VTR POR GP61 Default = 0x01 on VTR POR N/A SMSC DS – LPC47M192 (hex) 45 General Purpose I/0 bit 5.6 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nCTS2 ...

Page 162

... GP5 Default = 0x00 on VTR POR Bit 3 is reset on VCC POR, PCI Reset and VTR POR GP6 Default = 0x00 on VTR POR N/A SMSC DS – LPC47M192 (hex) 4B General Purpose I/0 Data Register 1 Bit[0] GP10 (R/W) Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 ...

Page 163

... REG OFFSET NAME FAN1 Default=0x00 on VTR POR FAN2 Default = 0x00 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 56 FAN Register 1 Bit[0] Fan Control (R/W) 1=FAN1 pin is high 0=bits[6:1] control the duty cycle of the FAN1 pin. Bit[6:1] Duty Cycle Control for FAN1 Control the duty cycle of the FAN1 pin ...

Page 164

... Register Default = 0x00 on VTR POR Fan1 Preload Register Default = 0x00 on VTR POR SMSC DS – LPC47M192 DESCRIPTION (hex) 58 Fan Control Register Bit[0] Fan 1 Clock Source Select (R/W) This bit and the Fan 1 Clock Multiplier bit is used with The Fan 1 Clock Select bit in the Fan 1 register (0x56) to determine the fan speed F Speed Control and Monitoring” ...

Page 165

... VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be set on a VCC POR. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0). Note 7: These bits are R/W but have no effect on circuit operation. SMSC DS – LPC47M192 DESCRIPTION (hex) 5C Fan Preload Register 2 Bit[7:0] The FAN2 tachometer preload ...

Page 166

... System Elements 9.1.1 PRIMARY CONFIGURATION ADDRESS DECODER After a hard reset (PCI_RESET# pin asserted) or Vcc Power On Reset the LPC47M192 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M192 into Configuration Mode. ...

Page 167

... MOV MOV OUT Notes: HARD RESET: PCI_RESET# pin asserted. SOFT RESET: Bit 0 of Configuration Control register set to one. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) SMSC DS – LPC47M192 DX,02EH AX,055H DX,AL | DX,02EH AL,07H DX,AL ...

Page 168

... Table 64 – LPC47M192 Configuration Registers Summary INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x60 0x21 R 0x22 R/W 0x00 0x23 R/W 0x00 0x24 R/W 0x44 Sysopt=0: 0x26 R/W 0x2E Sysopt=1: 0x4E Sysopt=0: 0x27 R/W 0x00 Sysopt=1: 0x00 0x28 ...

Page 169

... R/W 0x61 R/W 0x30 0x70 R/W 0x05 Note : Reserved registers are read-only, reads return 0. Note 1. Bits[6:5] of KRESET and GateA20 Select register reset on VTR POR only. SMSC DS – LPC47M192 SOFT VCC POR VTR POR RESET 0x00 0x00 0x00 0x00 0x00 0x00 ...

Page 170

... Device Rev Hard wired = Current Revision PowerControl Default = 0x00 on VCC POR, VTR POR, SOFT RESET and PCI RESET SMSC DS – LPC47M192 Table 65 - Chip Level Registers ADDRESS DESCRIPTION Chip (Global) Control Registers 0x00 - Reserved - Writes are ignored, reads return 0. 0x01 0x02 W The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit Soft Reset. Refer to the “ ...

Page 171

... VCC POR and PCI RESET Default = 0x00 on VCC POR, SOFT RESET and PCI RESET Chip Level Vendor Defined SMSC DS – LPC47M192 ADDRESS DESCRIPTION 0x23 R/W Bit[0] FDC (See Note in the “FDC Power Management” section) Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port ...

Page 172

... CR27 changes the base address). The configuration address is only reset to its default address upon a PCI Reset or Vcc POR. Note : The default configuration address is either 02Eh or 04Eh, as specified by the SYSOPT pin. SMSC DS – LPC47M192 ADDRESS DESCRIPTION 0x2A R/W Test Modes: Reserved for SMSC ...

Page 173

... VCC POR, VTR POR, PCI RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, PCI RESET and SOFT RESET SMSC DS – LPC47M192 Table 66 - Logical Device Registers ADDRESS DESCRIPTION (0x30) Bits[7:1] Reserved, set to zero. Bit[ Activates the logical device currently selected through the Logical Device # register ...

Page 174

... Note 3 : The default value of the Primary Interrupt Select register for logical device 0 is 0x06. Note 4 : The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 3 and 5 is 0x04. SMSC DS – LPC47M192 ADDRESS DESCRIPTION (0x74,0x75) Only 0x74 is implemented for FDC and Parallel port ...

Page 175

... Port 0x04 Serial Port 1 0x60,0x61 0x05 Serial Port 2 0x60,0x61 0x06 Reserved 0x07 KYBD 0x08 Reserved 0x09 Game Port 0x60,0x61 SMSC DS – LPC47M192 BASE I/O RANGE (Note 1) [0x0100:0x0FF8 SRA +1 : SRB ON 8 BYTE +2 : DOR BOUNDARIES +3 : TDR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR n/a n/a n/a ...

Page 176

... IRQs are disabled if not used/selected by any Logical Device. Refer to Note A. nSMI must be disabled to use IRQ2. All IRQ’s are available in Serial IRQ mode. Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06. SMSC DS – LPC47M192 BASE I/O RANGE (Note 1) ...

Page 177

... Keyboard Controller: Refer to the KBD section of this spec. e) MPU-401: Refer to the MPU-401 section of this spec. SMSC DS – LPC47M192 DEFINITION Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active IRQ ...

Page 178

... Default = 0x0E on VCC POR, VTR POR and PCI RESET FDD Option Register Default = 0x00 on VCC POR, VTR POR and PCI RESET SMSC DS – LPC47M192 REG INDEX DEFINITION 0xF0 R/W Bit[0] Floppy Mode = 0 Normal Floppy Mode (default Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode ...

Page 179

... Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note : The LPC47M192 supports two floppy drives 0xF3 R Reserved, Read as 0 (read only) 0xF4 R/W Bits[1:0] Drive Type Select: DT1, DT0 ...

Page 180

... Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note : If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt. SMSC DS – LPC47M192 REG INDEX DEFINITION 0xF0 R/W ...

Page 181

... Table 74 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 Default = 0x00 on VCC POR, VTR POR and PCI RESET SMSC DS – LPC47M192 UART Interrupt Operation Table REG INDEX DEFINITION 0xF0 R/W Bit[0] MIDI Mode = 0 MIDI support disabled (default MIDI support enabled ...

Page 182

... NAME REG INDEX Bits[6:5] reset on VTR POR only SMSC DS – LPC47M192 DEFINITION 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect KDAT signal to keyboard wakeup (PME) logic ...

Page 183

... Primary Base I/O Address Low Byte Default = 0x30 on PCI RESET, SOFT RESET, VCC POR and VTR POR SMSC DS – LPC47M192 DEFINITION 0xF0 Bit[0] (CLK32_PRSN) (R/W) 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded) Bit[1] SPEKEY_EN. This bit is used to turn the logic for the “ ...

Page 184

... Read Only 22 Read Only 23 Read Only 24 Read Only 25 Read Only 26 Read Only 27 Read Only 2B Read / Write 2C Read / Write SMSC DS – LPC47M192 TYPE DEFAULT REGISTER W - Internal Address Register R/W - Value or Limit Registers R 0x55 Company ID R 0x20 Stepping Number and Version R/W 0x08 ...

Page 185

... The offset register is configured for the external temperature channel by default. It may be switched to the internal channel by setting bit 4 of the Special Function Register to 1. Note 3: The default values of the High and Low limit registers should be written after power on reset. SMSC DS – LPC47M192 DESCRIPTION +Vccp High Limit +Vccp Low Limit +3 ...

Page 186

... HVCC POR and Initialization Bit[4] is self-clearing SMSC DS – LPC47M192 DESCRIPTION Bits[7:0] This location contains the identification number which will be used by software to determine analog voltage curves. Bits[7:0] This location contains the stepping number of the part in the lower four bits of the register [3:0]. The upper four bits reflect the Version Number [7:4] ...

Page 187

... Initialization Interrupt Status 42 Register 2 (R) Default = 0x00 on HVCC POR and Initialization SMSC DS – LPC47M192 DESCRIPTION Bit[0] +2.5v_Error A one indicates a High or Low limit has been reached or exceeded. Bit[1] Vccp_Error A one indicates a High or Low limit has been reached or exceeded. Bit[2] +3.3v_Error A one indicates a High or Low limit has been reached or exceeded ...

Page 188

... Debug 4B Register (R) Default = 0x00 on HVCC POR and Initialization SMSC DS – LPC47M192 DESCRIPTION Bits[3:0] VID[3:0] The VID[3:0] inputs from Pentium/PRO power supplies to indicate the operating voltage (e.g. 1.5V to 2.9V). Bits[6:4] Reserved Bit[7] RESET# Enable 0= Enables A0 pin for lowest order programmable bit of SMBus ...

Page 189

... HVCC POR and Initialization Note: Reserved bits are Read-Only and return ‘0’ when read. Reserved1 bits are Read-Only and return a ‘1’ when read. SMSC DS – LPC47M192 DESCRIPTION This register is used for the digital test mode test. Bit[0] Low-Power Mode Select ...

Page 190

... Monitoring Mode Sleep Mode Shutdown Mode 11.2.3 OPERATING TEMPERATURE Operating Temperature Range 11.2.4 OPERATING VOLTAGE RATINGS Supply Voltage (V+) VIN Voltage Range (Digital pins) SMSC DS – LPC47M192 +5.5 V (max) -0.3V to (HVcc+0.3V) (Except analog inputs) -0.3V to (Channel Voltage + 10%) HVcc-10% <HVcc HVcc+10% ±2% (max) ...

Page 191

... High Output Level OD12 Type Buffer Low Output Level High Output Level OD14 Type Buffer Low Output Level High Output Level OP14 Type Buffer Low Output Level High Output Level SMSC DS – LPC47M192 SUPER I/O BLOCK MIN TYP MAX V ILI V 2.0 IHI ...

Page 192

... High Output Level IOD16 Type Buffer Low Input Level High Input Level Low Output Level High Output Level PCI Type Buffers 3.3V PCI 2.1 Compatible. (PCI_ICLK, PCI_I, PCI_O, PCI_IO) SMSC DS – LPC47M192 SUPER I/O BLOCK MIN TYP MAX V ILI V 2.0 IHI ...

Page 193

... LPC Bus Pins (LAD[3:0], LDRQ#, LPCPD#, LFRAME#) Input High Current ILEAK Input Low Current ILEAK V Supply Current Active CC Trickle Supply Voltage V Supply Current Active TR Reference Voltage V Supply Current Active REF SMSC DS – LPC47M192 SUPER I/O BLOCK MIN TYP MAX (Note min ...

Page 194

... Input Resistance ADC Resolution I Type Input Buffer M (A0, VID0-VID4, XNOR_IN) Low Input Level High Input Level I Type Input Buffer M (SCLK) Low Input Level High Input Level Hysteresis SMSC DS – LPC47M192 HARDWARE MONITORING BLOCK MIN TYP -3 -2 ± ±1 90 5.5 TUE DNL ±1 PSS ± ...

Page 195

... Low Input Level High Input Level Hysteresis Low Output Level High Output Level Leakage Current (ALL - Digital) Input High Current ILEAK Input Low Current ILEAK Digital Input Capacitance SMSC DS – LPC47M192 HARDWARE MONITORING BLOCK MIN TYP -3 -2 ± ±1 90 5.5 V ...

Page 196

... The input and output capacitance applies to both the Super I/O Block and the Hardware Monitoring Block digital pins. o CAPACITANCE 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance Note: The input capacitance of a port is measured at the connector pins. SMSC DS – LPC47M192 HARDWARE MONITORING BLOCK MIN TYP -3 -2 ± ±1 90 5.5 applies when V is active ...

Page 197

... TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. SER_IRQ LAD# [3:0] nSTROBE SMSC DS – LPC47M192 CAPACITANCE TOTAL (pF) NAME 50 50 LDRQ# 50 nDIR 240 nSTEP 240 nDS0 240 nDS1 240 PD[0:7] 240 240 nALF 240 J1X-Y 50 J2X-Y ...

Page 198

... Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32KHZ t2 Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown) SMSC DS – LPC47M192 t 1 FIGURE 12 - POWER-UP TIMING MIN 300 100 125 t1 t2 FIGURE 13 - INPUT CLOCK TIMING ...

Page 199

... NAME t1 Period t2 High Time t3 Low Time t4 Rise Time t5 Fall Time PCI_RESET# NAME t1 PCI_RESET# width SMSC DS – LPC47M192 FIGURE 14 - PCI CLOCK TIMING DESCRIPTION t1 FIGURE 15 - RESET TIMING DESCRIPTION Page 199 DATASHEET t4 t2 MIN TYP MAX UNITS 30 33.3 nsec 12 nsec 12 nsec 3 nsec 3 nsec MIN ...

Page 200

... FIGURE 17 - INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME t1 Input Set Up Time to CLK – Bused Signals t2 Input Hold Time from CLK PCI_CLK LFRAME# LAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 SMSC DS – LPC47M192 t1 t2 DESCRIPTION t1 Inputs Valid DESCRIPTION Address Data TAR FIGURE 18 - I/O WRITE Page 200 ...

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