FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet
FDC37C78-HT
Specifications of FDC37C78-HT
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FDC37C78-HT Summary of contents
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... Floppy Disk Controller • 3.3/5 Volt Operation • Intelligent Auto Power Management • 2.88MB FDC37C78 Floppy Disk Controller Licensed CMOS 765B Floppy Disk - Controller - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Supports Two Floppy Drives Directly - Supports Vertical Recording Format ...
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... FEATURES...............................................................................................................................................1 GENERAL DESCRIPTION .......................................................................................................................3 PIN CONFIGURATION.............................................................................................................................4 DESCRIPTION OF PIN FUNCTIONS ......................................................................................................6 FUNCTIONAL DESCRIPTION ...............................................................................................................10 FDC37C78 REGISTERS ..................................................................................................................10 HOST PROCESSOR INTERFACE ..................................................................................................10 FLOPPY DISK CONTROLLER .........................................................................................................11 FLOPPY DISK CONTROLLER INTERNAL REGISTERS.................................................................11 COMMAND SET/DESCRIPTIONS .........................................................................................................29 INSTRUCTION SET ...............................................................................................................................32 AUTO POWER MANAGEMENT.............................................................................................................58 CONFIGURATION..................................................................................................................................62 OPERATIONAL DESCRIPTION.............................................................................................................71 MAXIMUM GUARANTEED RATINGS ..............................................................................................71 DC ELECTRICAL CHARACTERISTICS ...........................................................................................71 TIMING DIAGRAMS ...............................................................................................................................75 ...
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... Software Configurable Logic (SCL) for ease of use. Use of the SCL feature allows programmable system functions of FDC The FDC37C78 does not require any external filter components, and is, therefore easy to use 100% and offers lower system cost and reduced board and PC/AT area ...
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... VSS 6 VCC VCC PIN CONFIGURATION FDC37C78 nMTR0 35 nDS1/PD 34 nMTR1/IDLE 33 nDIR 32 VCC 31 nSTEP 30 VSS 29 nHDSEL 28 nWGATE 27 nWDATA 26 MEDIA_ID1 MEDIA_ID0 25 ...
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... PIN # Note: “n” denotes active low signal. FDC37C78 PIN OUT FDC37C78 48 Pin FDC NAME PIN # NAME nDACK 25 MEDIA_ID0 D0 26 MEDIA_ID1 D1 27 nWDATA D2 28 nWGATE D3 29 nHDSEL VSS 30 VSS VCC 31 nSTEP D4 32 VCC D5 33 nDIR D6 34 nMTR1/IDLE D7 35 nDS1/PD VCC 36 nMTR0 ...
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DESCRIPTION OF PIN FUNCTIONS DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL HOST PROCESSOR INTERFACE 2-5, Data Bus 0-7 D0-D7 8-11 46 I/O Read nIOR 47 I/O Write nIOW 44-42 I/O Address A0-A2 48 DMA Request DRQ 1 n DMA ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 38 Reset RESET 21 Read Disk Data nRDATA 27 Write nWDATA Data 29 Head nHDSEL Select 33 Direction nDIR Control 31 Step Pulse nSTEP 20 Disk Change nDSKCHG 22, DRVDEN 0, DRVDEN0, ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 25, Media ID0, MEDIA_ID0, 26 Media ID1 MEDIA_ID1 28 Write Gate nWGATE 15 Track 0 nTRK0 16 Index nINDEX 17 nWrite Protected nWRTPRT 36 nMotor On 0 nMTR0 37 nDrive Select 0 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 40 CLOCK CLOCK 12, 19, Power 18, 30, Ground GND 41 BUFFER TYPE DESCRIPTIONS .3 Note: These values are for 3 V ...
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... The address map, shown below in Table 1, shows the addresses of the different blocks of the FDC37C78 immediately after power up. Some addresses are used to access more than one register. Table 1 - FDC37C78 Block Addresses ADDRESS +0, +1 Base +0,1 Base +[2:5, 7] Note 1: Configuration registers can only be modified in configuration mode, refer to the configuration register description for more information ...
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... R The FDC37C78 is 82077AA using SMSC's proprietary floppy disk controller core. FLOPPY DISK CONTROLLER REGISTERS The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also 7 6 MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These ...
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... TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC37C78 does not require its characteristics modified for tape support. contents of this register are not used internal to the device. The TDR is unaffected by a software reset ...
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Table 7 - External Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 SEL0 ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any RQM DIO NON DMA BIT ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a high impedance state during ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY 7 6 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 13 for the appropriate ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 00 - Normal termination of command. 5 ...
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BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writable 0 MA Missing Address Mark * D= Decimal Table 15 - Status Register ...
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Table 16 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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... DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC37C78, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. ...
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DMA TRANSFERS DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. ...
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A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then ...
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If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector hardware TC was received. The only difference between ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 18 - Description of Command Symbols SYMBOL NAME field. HLT Head Load Time The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. ...
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Table 18 - Description of Command Symbols SYMBOL NAME modified set defined in the Lock command. PCN Present Cylinder The current position of the head at the completion of Sense Interrupt Number Status ...
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INSTRUCTION SET PHASE R Command W MT MFM Execution Result Table 19 - Instruction Set READ DATA DATA BUS D5 D4 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command ─── SRT ─── W ────── HLT ────── W RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ──── SRT ──── LOCK R 0 EIS EFIFO R RELATIVE SEEK DATA ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 ...
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PHASE R Command PHASE R ───── Invalid Codes ───── Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 23 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR TRANSFERRED TO MT HEAD HOST Less than EOT 0 0 Equal to EOT 1 Less than EOT Equal to EOT Less than EOT 1 0 Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 26 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 512 Drives 256 MFM 512 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Issue Read/Write command. The Seek command does not have a result phase. Therefore highly recommended that the Sense Interrupt Status command be issued after the Seek command to terminate it and to provide verification of the head ...
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Table 28 - Drive Control Delays (ms 500K 0 64 128 256 112 224 F 60 120 240 0 ...
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Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value returned as the result byte. Relative Seek The command is coded the same as for ...
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Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 31 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a ...
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When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular ...
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... LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37C78 was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk controllers ...
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... If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC37C78 resumes operation as though it was never in powerdown. Besides activating the RESET pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1 ...
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... PC systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the FDC37C78 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are ...
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Table 30 - PC/AT Available Registers Base + Address Access to these registers DOES NOT wake up the part 00H 01H 02H 03H 04H 06H 07H 07H Access to these registers wakes up the part 04H 05H Note 1: Writing ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 32 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins RDATA ...
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The configuration of the chip is programmable through software selectable registers. CONFIGURATION REGISTER ADDRESS The Configuration Registers are located at address offset +0 and +1 with nCS active. CONFIGURATION REGISTERS The configuration registers are used to select programmable options of ...
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ENTER CONFIGURATION MODE ;-----------------------------' MOV DX,3F0H MOV AX,055H ; CLI ; disable interrupts OUT DX,AL OUT DX,AL STI ; enable interrupts ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx | ;-----------------------------' MOV DX,3F0H MOV AL,00H OUT DX,AL ; Point to CR0 MOV ...
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Table 33 - Configuration Registers Default DB7 DB6 28H CR00 Valid Reserved 90H CR01 Lock CRx 00H CR02 Reserved 70H CR03 Reserved IDENT 00H CR04 00H CR05 Reserved EXTx4 FFH CR06 Floppy Drive D 00H CR07 Auto Power Management 00H ...
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CR00 This register can only be accessed when the chip is in the Configuration Mode and after the CSR has been initialized to 00H. The default value of this register after power up is 28H. BIT NO. BIT NAME 0:1 ...
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CR02 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 02H. The default value of this register after power up is 00H. BIT NO. BIT NAME 0:7 Reserved CR03 This register ...
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CR05 This register can only be accessed in to 05H. The default value after power up is 00H. Table 39 - CR05- Floppy Disk Extended Setup Register BIT NO. BIT NAME 0,1 Reserved 2 FDC DMA Mode 4,3 DenSel 5 ...
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BIT NO. BIT NAME 0,1 Floppy Boot Media ID0 2 Polarity Media ID1 3 Polarity 4:6 Reserved 7 Floppy Disk Enable CR08 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to ...
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CR0D This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0DH. This register is read only. This is the Device ID. The default value of this register after power up is ...
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CR1F This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 1FH. The default value of this register after power up is 00H. This register indicates the Drive Type used for each ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ..............................................................................................0 Storage Temperature Range .............................................................................................. -55 Lead Temperature Range (soldering, 10 seconds).........................................................................+325 Positive Voltage on any pin, with respect to Ground .................................................................... V Negative Voltage on any pin, with respect to Ground ...
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PARAMETER SYMBOL I/O12 Type Buffer V Low Output Level OL V High Output Level OH Output Leakage I OL O12 Type Buffer V Low Output Level OL V High Output Level OH I Output Leakage OL OD20 Type Buffer V ...
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PARAMETER SYMBOL I Input Buffer CLK V Low Input Level ILCK V High Input Level IHCK Input Leakage I Low Input Leakage IL I High Input Leakage IH I/O12 Type Buffer Low Output Level V OL High Output Level V ...
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Output Capacitance C OUT AC ground ...
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TIMING DIAGRAMS nCS t1 nIOR DATA (D0-D7) BUSY IRQ Parameter t1 nCS Set Up to nIOR Low t2 nIOR Width t3 nCS Hold from nIOR High Data Access Time from nIOR Low t4 t5 Data to Float Delay from nIOR ...
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DATA DATA VALID (D0-D7) IRQ Parameter t1 nCS Set Up to nIOW Low t2 nIOW Width t3 nCS Hold from nIOW High Data Set Up Time to nIOW High t4 t5 Data Hold Time from nIOW ...
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DRQ, t1 nDACK t14 t11 t6 nIOR t5 or nIOW DATA (DO-D7) TC Parameter t1 nDACK Delay Time from DRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 DRQ Reset Delay from nDACK Low t4 nDACK ...
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X1 t4 nRESET Name Description Clock CycleTime for 24MHZ t1 Clock High Time/Low Time for t2 14.318MHZ Clock Rise Time/Fall Time (not shown) nRESET Low Time t6 NOTE 1: The nRESET low time is dependent upon the processor clock. ...
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Parameter t1 nDIR Set Up to nSTEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time After nSTEP t4 nSTEP Cycle Time t5 nDS0-1 ...
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FIGURE 8 – 48 PIN TQFP PACKAGE DIMENSIONS MIN NOMINAL 0.05 0.10 A2 1.35 1.40 D 8.80 9.00 D/2 4.40 4.50 D1 6.90 7.00 E 8.80 9.00 E/2 4.40 4.50 E1 6.90 7.00 H 0.09 ~ ...
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MIN NOMINAL ccc ~ ~ ccc ~ ~ Note 1: Controlling Unit: millimeter Note 2: Tolerance on the position of the leads is ± 0.04 mm maximum. Note 3: Package body dimensions D1 and E1 do not include the mold ...
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... CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37C78 Rev. 02-16-07 ...