ISP1760BE,557 NXP Semiconductors, ISP1760BE,557 Datasheet - Page 49
ISP1760BE,557
Manufacturer Part Number
ISP1760BE,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1760BE557.pdf
(111 pages)
Specifications of ISP1760BE,557
Package Type
LQFP
Pin Count
128
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
Table 51.
[1]
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Power Down Control register (address 0354h) bit allocation
8.3.11 Power Down Control register
R/W
R/W
R/W
R/W
15
31
23
0
0
1
7
1
reserved
Table 50.
This register is used to turn off power to the internal blocks of the ISP1760 to obtain
maximum power savings.
Bit
31 to 16
15 to 0
reserved
[1]
R/W
R/W
R/W
R/W
14
30
22
0
0
1
6
0
DMA Start Address register (address 0344h) bit description
[1]
Symbol
-
START_ADDR
_DMA[15:0]
BIASEN
R/W
R/W
R/W
R/W
13
29
21
0
5
1
0
1
Rev. 04 — 4 February 2008
Table 51
CLK_OFF_COUNTER[15:8]
Description
reserved
Start Address for DMA: The start address for DMA read or write
cycles.
CLK_OFF_COUNTER[7:0]
VREG_ON
PORT3_
R/W
R/W
PD
R/W
R/W
12
4
0
1
28
20
0
0
shows the bit allocation of the register.
OC3_PWR OC2_PWR OC1_PWR
PORT2_
R/W
R/W
PD
11
R/W
R/W
1
3
0
27
19
0
1
Embedded Hi-Speed USB host controller
VBATDET_
PWR
R/W
R/W
10
2
0
R/W
R/W
0
26
18
0
0
R/W
1
0
R/W
R/W
R/W
25
17
9
1
1
0
© NXP B.V. 2008. All rights reserved.
reserved
ISP1760
HC_CLK_EN
[1]
R/W
R/W
R/W
R/W
0
0
48 of 110
24
16
1
0
8
1
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