ISP1760BE,557 NXP Semiconductors, ISP1760BE,557 Datasheet - Page 78

• Manufacturer Part Number: ISP1760BE,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760BE,557

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 76.
ISP1760_4
Product data sheet
Bit
7 to 0
DW3
63
62
61
60
59
58
57
56 to 44 reserved
43 to 32 NrBytes
DW2
31 to 24 reserved
23 to 8
7 to 0
DW1
63 to 57 HubAddress
56 to 50 PortNumber
49 to 47 reserved
46
45 to 44 EPType[1:0]
Symbol
A
H
B
X
SC
reserved
DT
Transferred[11:0]
DataStart
Address[15:0]
[6:0]
[6:0]
S
SA[7:0]
Frame[7:0]
Start and complete split for isochronous: bit description
Access
SW — writes
(0
HW — writes
(1
After processing
SW — sets
HW — resets
HW — writes
HW — writes
HW — writes
SW — writes 0
HW — updates
-
HW — writes
SW — writes
-
HW — writes
-
SW — writes
SW — writes
SW — writes
SW — writes
-
SW — writes
SW — writes
1)
0)
Value
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 04 — 4 February 2008
Description
Specifies which SOF the start split needs to be placed.
For OUT token: When the frame number of bits DW2[7:3] matches
the frame number of the USB bus, these bits are checked for one
before they are sent for the SOF.
For IN token: Only SOF0, SOF1, SOF2 or SOF3 can be set
to 1. Nothing can be set for SOF4 and above.
Active: Write the same value as that in V.
Halt: The Halt bit is set when any microframe transfer status has a
stalled or halted condition.
Babble: This bit corresponds to bit 1 of Status0 to Status7 for every
microframe transfer status.
Transaction Error: This bit corresponds to bit 0 of Status0 to
Status7 for every microframe transfer status.
Start/Complete:
0 — Start split
1 — Complete split
-
Data Toggle: Set the Data Toggle bit to start for the PTD.
-
Number of Bytes Transferred: This field indicates the number of
bytes sent or received for this transaction.
-
Data Start Address: This is the start address for data that will be
sent or received on or from the USB bus. This is the internal
memory address and not the CPU address.
Bits 7 to 3 determine which frame to execute.
Hub Address: This indicates the hub address.
Port Number: This indicates the port number of the hub or
embedded TT.
-
This bit indicates whether a split transaction has to be executed:
0 — High-speed transaction
1 — Split transaction
Transaction type:
01 — Isochronous
…continued
Embedded Hi-Speed USB host controller
© NXP B.V. 2008. All rights reserved.
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