PDIUSBD12PWTM STEricsson, PDIUSBD12PWTM Datasheet
PDIUSBD12PWTM
Specifications of PDIUSBD12PWTM
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PDIUSBD12PWTM Summary of contents
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PDIUSBD12 USB peripheral controller with parallel bus Rev. 12 — 8 April 2010 1. General description The PDIUSBD12 is a cost- and feature-optimized USB peripheral controller normally used in microcontroller-based systems and communicates with the system microcontroller over ...
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... Table 1. Ordering information Commercial Package description product code PDIUSBD12PWAA TSSOP28; 28 leads; body width 4.4 mm PDIUSBD12PWTM TSSOP28; 28 leads; body width 4.4 mm CD00222704 Product data sheet USB peripheral controller with parallel bus Packing single tube dry pack 13 inch tape and reel non-dry pack Rev. 12 — ...
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Block diagram This is a conceptual block diagram and does not include each individual signal. Fig 1. Block diagram 5. Pinning information 5.1 Pinning Fig 2. Pin configuration CD00222704 Product data sheet USB peripheral controller with parallel bus UPSTREAM ...
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Pin description Table 2. Symbol DATA0 DATA1 DATA2 DATA3 GND DATA4 DATA5 DATA6 DATA7 ALE CS_N SUSPEND CLKOUT INT_N RD_N WR_N DMREQ DMACK_N EOT_N RESET_N GL_N XTAL1 XTAL2 V CC D− CD00222704 Product data sheet Pin description [1] Pin ...
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Table 2. Symbol D+ VOUT3.3 A0 [1] P: power or ground; A: analog; I: input; O: Output; O2: Output with 2 mA drive; OD4: Output open-drain with 4 mA drive; OD8: Output open-drain with 8 mA drive; IO2: Input and ...
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Functional description 6.1 Analog transceiver The integrated transceiver directly interfaces to USB cables through termination resistors. 6.2 Voltage regulator A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output ...
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GoodLink A good USB connection indication is provided through the GoodLink technology. During enumeration, the LED indicator will momentarily blink on corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be ...
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Direct Memory Access (DMA) transfer DMA allows an efficient transfer of a block of data between the host and local shared memory. Using a DMA Controller (DMAC), the data transfer between the main endpoint (endpoint 2) of the PDIUSBD12 ...
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The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In single address mode, the DMA transfer is done using the DREQ, DMACK_N, EOT_N, WR_N and RD_N control ...
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Table 3. Endpoint number Mode 0 (Non-ISO mode Mode 1 (ISO-OUT mode Mode 2 (ISO-IN mode Mode 3 (ISO-I/O mode [1] IN: input for the USB host; OUT: ...
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Main endpoint The main endpoint (endpoint number 2) is the primary endpoint for sinking or sourcing relatively large amounts of data. It implements the following features to ease this task: • Double buffering. This allows parallel operation between the ...
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Table 4. Name Set Endpoint Status Acknowledge Setup Clear Buffer Validate Buffer General commands Send Resume Read Current Frame Number 11. Command description 11.1 Command procedure There are three basic types of commands: initialization, data flow and general. Respectively, these ...
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Set Endpoint Enable Code (Hex) — D8 Transaction — write 1 B The generic or isochronous endpoints can only be enabled when the function is enabled using the Set Address/Enable command. GENERIC OR ISOCHRONOUS ENDPOINTS: Logic 1 indicates that ...
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Table 5. Bit Symbol ENDPOINT CONFIGURATION 4 SoftConnect 3 INTERRUPT MODE 2 CLOCK RUNNING 1 NO LAZYCLOCK For bit allocation, see Fig 7. Set Mode command, clock division factor byte: bit allocation CD00222704 Product data sheet Set ...
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Table 6. Bit Symbol 7 SOF-ONLY INTERRUPT MODE 6 SET_TO_ONE CLOCK DIVISION FACTOR 11.2.4 Set DMA Code (Hex) — FB Transaction — read or write 1 B The Set DMA command is followed by one data write ...
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Table 7. Bit Symbol 7 ENDPOINT INDEX 5 INTERRUPT ENABLE 6 ENDPOINT INDEX 4 INTERRUPT ENABLE 5 INTERRUPT PIN MODE 4 AUTO RELOAD 3 DMA DIRECTION 2 DMA ENABLE DMA BURST 11.3 Data flow commands Data flow ...
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This command indicates the origin of an interrupt. The endpoint interrupt bits (bits are cleared by reading the Endpoint Last Transaction Status register through Read Last Transaction Status command. The other bits are cleared after reading Interrupt ...
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Select Endpoint Code (Hex) — Transaction — read 1 B (optional) The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, ...
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For bit allocation, see Fig 13. Read Last Transaction Status register: bit allocation Table 9. Bit Symbol 7 PREVIOUS STATUS NOT READ 6 DATA0/1 PACKET 5 SETUP PACKET ERROR CODE 0 DATA RECEIVE/TRANSMIT SUCCESS Table 10. Error ...
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Read Buffer Code (Hex) — F0 Transaction — read multiple bytes (max. 130) The Read Buffer command is followed by a number of data reads that return contents of the selected endpoint data buffer. After each read, the internal ...
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When a packet is completely received, an internal endpoint buffer full flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller has read data, it should free the buffer using the Clear Buffer command. ...
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The microcontroller must send the Acknowledge Setup command to both the IN and OUT endpoints. 11.4 General commands 11.4.1 Send Resume Code (Hex) — F6 Transaction — none Sends an upstream resume signal for 10 ms. This command is normally ...
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Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg ...
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Table 14. Static characteristics (digital pins) Symbol Parameter V HIGH-level output voltage OH Leakage current I off-state output current OZ I leakage current L I suspend current S I supply current CC Table 15. Static characteristics (AI/O pins) Symbol Parameter ...
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Table 16. Dynamic characteristics (AI/O pins; full-speed) Ω pF 1 Symbol Parameter Receiver timing: t receiver data jitter tolerance to next transition JR1 t receiver data jitter tolerance ...
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Table 17. Dynamic characteristics (parallel interface) Symbol Parameter t write command to write data (WC − WD) Read timing t CS_N (DMACK_N) LOW to RD_N LOW time CLRL t RD_N HIGH to CS_N (DMACK_N) HIGH time RHCH t A0 valid ...
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CLRL t CLWL CS_N DMACK_N t AVRL t AVWL A0 WR_N DATA[7:0] RD_N DATA[7:0] Fig 18. Parallel interface timing (I/O and DMA) Table 18. Dynamic characteristics (DMA) Symbol Parameter Single-cycle DMA timing t DMACK_N HIGH to DMREQ HIGH time ...
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DMREQ DMACK_N RD_N/WR_N (1) EOT_N EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW. Fig 19. Single-cycle DMA timing DMREQ DMACK_N RD_N/WR_N Fig 20. Burst DMA timing DMACK_N RD_N/WR_N Fig 21. DMA terminated by EOT CD00222704 Product ...
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Test information The dynamic characteristics of the analog I/O ports (D+ and D−) as listed in were determined using the circuit shown in Fig 22. Load for D+ and D− CD00222704 Product data sheet USB peripheral controller with parallel ...
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Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 ...
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Abbreviations Table 19. Acronym ACPI CPU CRC DMA DMAC EMI FIFO ISO MMU NAK OD PID PLL POR RAM SCSI SIE SOF USB CD00222704 Product data sheet Abbreviations Description Advanced Configuration and Power Interface Central Processing Unit Cyclic Redundancy ...
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Revision history Table 20. Revision history Revision Release date 12 20100408 • Modifications: Updated the filename according to the latest standards. • Section 2 11 20090929 10 20090123 9 20060511 8 (9397 750 08969) 20011220 7 (9397 750 08117) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration . . ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 12 — 8 April 2010 PDIUSBD12 USB peripheral controller with parallel bus © ...