ISP1583BSGA STEricsson, ISP1583BSGA Datasheet
ISP1583BSGA
Specifications of ISP1583BSGA
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ISP1583BSGA Summary of contents
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ISP1583 Hi-Speed USB peripheral controller Rev. 11 — 20 November 2009 1. General description The ISP1583 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus (USB) peripheral controller. It fully complies with Rev. 2.0”, supporting data transfer at high-speed (480 ...
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High performance USB peripheral controller with integrated Serial Interface Engine (SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver Automatic Hi-Speed USB mode detection and Original USB fall-back mode Supports sharing mode Supports I/O voltage range of 1.65 V ...
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... ISP1583ET2UM [1] Contains solder ball material SAC405. [2] Contains solder ball material SAC105. 5. Marking Table 2. Commercial product code ISP1583BSUM ISP1583BSGA ISP1583ETUM ISP1583ET1TM ISP1583ET2UM [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1583_11 Product data sheet Packing 13 inch reel dry pack ...
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USB BUS 3.3 V SoftConnect 1.5 kΩ RPU 2 ST-ERICSSON RREF 6 HI-SPEED USB SIE/PIE TRANSCEIVER 12 kΩ 7 ...
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Pinning information 7.1 Pinning READY/IORDY Fig 2. Pin configuration ISP1583BS (top view) Fig 3. Pin configuration ISP1583ET and ISP1583ET2 (top view) ISP1583_11 Product data sheet terminal 1 index area AGND 1 2 RPU AGND ...
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Fig 4. Pin configuration ISP1583ET1 (top view) 7.2 Pin description Table 3. Pin description [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 AGND 1 D2 RPU AGND 5 - RREF 6 D1 RESET_N 7 ...
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Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 DACK 10 F1 DIOR 11 G2 DIOW 12 G1 DGND 13 H2 INTRQ 14 H1 READY IORDY INT 16 K1 [3] DA2 17 J2 CS_N 18 K2 ...
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Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 RW_N RD_N DS_N WR_N [3] CS0_N 21 J4 [3] CS1_N 22 K4 AD0 23 K5 AD1 24 J5 AD2 ...
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Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 MODE1 34 J10 DGND 35 H9 ALE/A0 36 H10 DATA0 37 G9 DATA1 38 G10 DATA2 39 F9 DATA3 40 F10 [ CC(I/O) DATA4 42 E10 ...
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Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 DATA10 48 A10 DATA11 49 A9 DATA12 50 B8 DATA13 51 A8 DATA14 52 B7 DATA15 CC(I/ BUS [4] VCC1V8 ...
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Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 BUS_ 62 B2 CONF/ [3] DA0 WAKEUP 63 A2 SUSPEND 64 C2 DGND - B9 DGND exposed die J9 pad [1] Symbol names ending with underscore N, for example, ...
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Functional description The ISP1583 is a high-speed USB peripheral controller. It implements the Hi-Speed USB or the Original USB physical layer, and the packet protocol layer. It concurrently maintains USB endpoints (control IN, control OUT, and ...
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Table 4. Endpoint identifier EP0SETUP EP0RX EP0TX EP1RX EP1TX EP2RX EP2TX EP3RX EP3TX EP4RX EP4TX EP5RX EP5TX EP6RX EP6TX EP7RX EP7TX The ISP1583 operates MHz crystal oscillator. An integrated 40 × PLL clock multiplier generates the internal ...
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Hi-Speed USB transceiver The analog transceiver directly interfaces to the USB cable through integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 kΩ ± between pin RREF and ground to ensure an accurate current mirror ...
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Any A-device, including laptop, can respond to SRP. Any B-device, including a standard USB peripheral, can initiate SRP. The ISP1583 is a device that can initiate SRP. 8.6 ST-Ericsson high-speed transceiver 8.6.1 ST-Ericsson Parallel Interface Engine (PIE) ...
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ST-Ericsson Serial Interface Engine (SIE) The ST-Ericsson SIE implements the full USB protocol layer completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit-stuffing ...
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Table 5. Bus configuration modes Pin PIO width DMA width BUS_CONF/ WIDTH = 0 DA0 LOW AD[7:0] D[7:0] HIGH A[7:0] and D[7:0] D[15:0] 8.12 Pins status Table 6 illustrates the behavior of ISP1583 pins with V operating conditions. Table 6. ...
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Interrupt 8.13.1 Interrupt output pin The Interrupt Configuration register of the ISP1583 controls the behavior of the INT output pin. The polarity and signaling mode of the INT pin can be programmed by setting bits INTPOL and INTLVL of ...
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DMA Interrupt Reason register GDMA_STOP EXT_EOT INT_EOT BSY_DONE TF_RD_DONE CMD_INTRQ_OK OR DMA Interrupt Enable register IE_GDMA_STOP IE_EXT_EOT IE_INT_EOT IE_BSY_DONE IE_TF_RD_DONE IE_CMD_INTRQ_OK Fig 5. Interrupt logic Interrupt Enable register IEBRST IESOF IEDMA IEP7RX ...
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Interrupt control Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior of this bit is given in The following illustrations are only applicable for level trigger. Event A: When an interrupt event ...
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The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see Fig 7. Resistor and electrolytic or tantalum capacitor needed for V Fig 8. Oscilloscope reading: no resistor and capacitor in the network Fig 9. Oscilloscope reading: ...
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Power-on reset The ISP1583 requires a minimum pulse width of 500 μs. The RESET_N pin can either be connected to V externally controlled (by the microcontroller, ASIC, and so on). When V connected to the RESET_N pin, internal pulse ...
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Power supply The ISP1583 can be powered by 3.3 V ± 0.3 V, and from 1. 3 the interface. For details, see 3.3 V-to-1.8 V voltage regulator provides a 1.8 V supply voltage for the ...
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Power-sharing mode V Fig 13. Power-sharing mode As can be seen in the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V supplied through the power source of the system. When the USB cable is ...
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Table 9. ISP1583 operation Normal bus operation Core power is lost Table 10. ISP1583 operation Clock will wake up: After a resume and After a bus reset Core power is lost Table 11. ISP1583 operation Back voltage is not measured ...
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Self-powered mode V Fig 15. Self-powered mode In self-powered mode, V Table 13. ISP1583 operation Normal bus operation No pull [1] When the USB cable is removed, SoftConnect is disabled. Table 14. ISP1583 operation Clock will ...
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Table 16. ISP1583 operation SRP is not applicable SRP is possible 8.16.3 Bus-powered mode 1. 3 Fig 16. Bus-powered mode In bus-powered mode (see the 5 V-to-3.3 V voltage regulator. The input to the regulator is ...
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Table 19. ISP1583 operation Back voltage is not measured in this mode Power is lost Table 20. ISP1583 operation SRP is not applicable Power is lost ISP1583_11 Product data sheet Operation truth table for back voltage compliance V CC(3V3) 3.3 ...
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Register description Table 21. Register overview Name Destination Initialization registers Address device Mode device Interrupt Configuration device OTG device Interrupt Enable device Data flow registers Endpoint Index endpoints Control Function endpoint Data Port endpoint Buffer Length endpoint Buffer Status ...
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Table 21. Register overview …continued Name Destination Task File 1F0 ATAPI peripheral Task File 1F1 ATAPI peripheral Task File 1F2 ATAPI peripheral Task File 1F3 ATAPI peripheral Task File 1F4 ATAPI peripheral Task File 1F5 ATAPI peripheral Task File 1F6 ...
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Buffer Length • Buffer Status • Control Function • Data Port • Endpoint MaxPacketSize • Endpoint Type Remark: Write zero to all reserved bits, unless otherwise specified. 9.2 Initialization registers 9.2.1 Address register (address: 00h) This register sets the ...
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Table 24. Mode register: bit allocation Bit 15 14 Symbol TEST2 TEST1 Reset - - Bus reset - - Access R R Bit 7 6 Symbol CLKAON SNDRSU Reset 0 0 Bus reset unchanged 0 Access R/W R/W [1] Value ...
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Table 25. Bit Symbol 3 GLINTENA 2 WKUPCS 1 PWRON 0 SOFTCT The status of the chip is shown in Table 26. Bus state V on BUS V off BUS 9.2.3 Interrupt Configuration register (address: 10h) This 1-byte register determines ...
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Table 27. Interrupt Configuration register: bit allocation Bit 7 6 Symbol CDBGMOD[1:0] Reset 1 1 Bus reset 1 1 Access R/W R/W Table 28. Bit Symbol CDBGMOD[1: DDBGMODIN[1: DDBGMODOUT[1:0] Data Debug ...
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Table 31. Bit Symbol Description BSESS VALID 3 INIT COND 2 DISCV OTG [1] No interrupt is designed for OTG. The V pulsing. When OTG is in progress, the V ...
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Session Request Protocol (SRP) The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by V pulsing. The ISP1583 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to ...
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Table 32. Interrupt Enable register: bit allocation Bit 31 30 Symbol Reset - - Bus reset - - Access - - Bit 23 22 Symbol IEP6TX IEP6RX Reset 0 0 Bus reset 0 0 Access R/W R/W Bit 15 14 ...
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Table 33. Bit 9.3 Data flow registers 9.3.1 Endpoint Index register (address: 2Ch) The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 ...
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Table 35. Bit Symbol EP0SETUP ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of 0 DIR Table 36. Buffer name SETUP Control OUT Control IN Data OUT Data IN 9.3.2 ...
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Table 38. Bit Symbol CLBUF 3 VENDP 2 DSEN 1 STATUS Status Acknowledge: Only applicable for control IN or OUT. 0 STALL 9.3.3 Data Port register (address: 20h) This 2-byte register provides direct access for ...
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The data packet will then be sent on the next IN token. When it is necessary to validate the endpoint whose byte count is less than MaxPacketSize, it can be done using the Control Function register ...
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Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register need not be filled. This is because the transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets ...
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Table 43 shows the bit allocation of the Buffer Status register. Table 43. Buffer Status register: bit allocation Bit 7 6 Symbol Reset - - Bus reset - - Access - - Table 44. Bit Symbol ...
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Table 46. Bit The ISP1583 supports all the transfers given in Rev. 2.0”. Each programmable FIFO can be independently configured using its Endpoint MaxPacketSize register (R/W: 04h), but the total physical ...
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Table 48. Bit Symbol NOEMPKT 3 ENABLE 2 DBLBUF ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type. 9.4 DMA registers Two types of Generic DMA transfers and three types of IDE-specified ...
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In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. The DMA transfer will start once the DMA command is issued. ...
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Table 49. Control bits DMA Hardware register ENDIAN[1:0] EOT_POL MASTER ACK_POL, DREQ_POL, WRITE_POL, READ_POL Table 50. Control bits DMA Configuration register ATA_MODE DMA_MODE[1:0] PIO_MODE[2:0] DMA Hardware register MASTER Remark: The DMA bus defaults to 3-state, until a DMA command is ...
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Table 52. Bit Table 53. Code 00h 01h 02h to 05h 06h 07h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h ISP1583_11 Product data sheet DMA Command register: bit description Symbol Description DMA_CMD[7:0] DMA command code, see PIO ...
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Table 53. Code 11h 12h 13h 14h to 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h to FFh 9.4.2 DMA Transfer Counter register (address: 34h) This 4-byte register sets up the total byte count for a DMA transfer ...
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If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when it reaches zero. Table 54. DMA Transfer Counter register: bit allocation Bit 31 30 Symbol Reset 0 0 Bus reset 0 0 Access ...
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Bit 7 6 Symbol DIS_ XFER_CNT Reset 0 - Bus reset 0 - Access R/W - Table 57. Bit [1] The ...
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PIO read or write that started using the DMA Command register only performs 16-bit transfer. 9.4.4 DMA Hardware register (address: 3Ch) The DMA Hardware register consists of 1 byte. The bit allocation is shown in This register determines the ...
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Table 59. Bit Symbol 2 DREQ_POL 1 WRITE_POL Write Polarity: Selects the DIOW strobe polarity. 0 READ_POL 9.4.5 Task File registers (addresses: 40h to 4Fh) These registers allow direct access to the internal registers of an ATAPI peripheral using PIO ...
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In 8-bit bus mode, 16-bit Task File register 1F0 requires two consecutive write/read accesses before the proper PIO write/read is generated on the IDE interface. The first byte is always the lower byte (LSByte). Other Task File registers can directly ...
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Table 67. Task File 1F5 register (address: 4Ch): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH. Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W Table ...
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DMA Interrupt Reason register (address: 50h) This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. On ...
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Table 73. Bit Table 74. INT_EOT 9.4.7 DMA Interrupt Enable register (address: 54h) This 2-byte register controls the interrupt generation of the source bits in the DMA Interrupt Reason register (see description is given ...
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Table 76. DMA Endpoint register: bit allocation Bit 7 6 Symbol Reset - - Bus reset - - Access - - Table 77. Bit The DMA Endpoint register must not reference the endpoint ...
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Fig 17. Programmable strobe timing 9.4.10 DMA Burst Counter register (address: 64h) Table 80 shows the bit allocation of the 2-byte register. Table 80. DMA Burst Counter register: bit allocation Bit 15 14 Symbol reserved Reset - - Bus reset ...
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Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt Reason register, followed by writing logic 1 to ...
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Table 83. Bit 9.5.2 Chip ID register (address: 70h) This read-only register contains the chip identification and hardware version numbers. The firmware must check this information to determine functions ...
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Table 85. Bit 9.5.3 Frame Number register (address: 74h) This read-only register contains the frame number of the last successfully received Start-Of-Frame (SOF). The register contains 2 bytes, and the bit ...
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Table 89. Bit 9.5.5 Unlock Device register (address: 7Ch) To protect registers from getting corrupted when the ISP1583 goes into suspend, the write operation is disabled if bit PWRON in the Mode register is ...
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Table 92. Test Mode register: bit allocation Bit 7 6 Symbol FORCEHS Reset 0 - Bus reset unchanged - Access R/W - Table 93. Bit Symbol 7 FORCEHS FORCEFS 3 PRBS 2 KSTATE 1 JSTATE ...
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Limiting values Table 94. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) CC(3V3) V input/output supply voltage CC(I/O) V input voltage I I latch-up current lu V electrostatic ...
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Table 96. Static characteristics: supply pins ± 3 CC(3V3) GND Symbol Parameter I supply current on pin V CC(I/O) Regulated supply voltage V supply voltage (1.8 V) CC(1V8) [1] I ...
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Table 99. Static characteristics: analog I/O pins DP and DM ± 3 CC(3V3) GND Symbol Parameter Schmitt-trigger inputs V positive-going threshold voltage th(LH) V negative-going threshold voltage th(HL) V hysteresis ...
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Table 101. Dynamic characteristics: analog I/O pins DP and DM ± 3 CC(3V3) GND Figure 38; unless otherwise specified. Symbol Parameter Driver characteristics Full-speed mode t rise time FR t ...
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T PERIOD +3.3 V differential data lines the bit duration corresponding to the USB data rate. PERIOD Fig 19. Receiver differential data jitter Fig 20. Receiver SE0 width tolerance 13.1 Register access timing Remark: In ...
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Table 102. ISP1583 register access timing parameters: separate address and data buses CC(I/O) CC(3V3) Symbol Parameter t CS_N LOW to RW_N/RD_N LOW delay SLRL Writing t DS_N/WR_N LOW ...
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DS_N/WR_N, RW_N/RD_N READY/IORDY Fig 22. ISP1583 ready signal timing 13.1.1.2 Freescale mode MODE0/DA1 = LOW: Freescale mode; see Table 103. ISP1583 register access timing parameters: separate address and data buses 3.3 ...
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CS_N AD [ 7:0 ] (read) DATA [ 15 (write) DATA [ 15 I1VI2L DS_N/WR_N RW_N/RD_N Fig 23. ISP1583 register access timing: separate address and data buses (Freescale mode) DS_N/WR_N READY/IORDY Fig 24. ISP1583 ready signal ...
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Programmable polarity: shown as active LOW. Remark: EOT must be valid for 36 ns (minimum) when pins RW_N/RD_N and DS_N/WR_N are active. Fig 25. EOT timing in generic processor mode 13.1.2 Split bus mode 13.1.2.1 ALE function 8051 mode ...
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CS_N (read 7:0 ] address RW_N/RD_N (write 7:0 ] DS_N/WR_N t AVLL ALE/A0 Fig 26. ISP1583 register access timing: multiplexed address/data bus (8051 mode) Freescale mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = ...
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CS_N (read 7:0 ] address (write 7 I1VLL DS_N/WR_N RW_N/RD_N ALE/A0 Fig 27. ISP1583 register access timing: multiplexed address/data bus (Freescale mode) 13.1.2.2 A0 function 8051 mode • BUS_CONF/DA0 = LOW: split bus mode ...
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Table 106. ISP1583 register access timing parameters: multiplexed address/data bus CC(I/O) CC(3V3) Symbol Parameter t DS_N/WR_N HIGH (address) to DS_N/WR_N WHWH HIGH (data) delay General T read or ...
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Table 107. ISP1583 register access timing parameters: multiplexed address/data bus CC(I/O) CC(3V3) Symbol Parameter t DS_N/WR_N HIGH to CS_N HIGH delay RHSH t DS_N/WR_N LOW pulse width RLRH ...
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A0WL ALE/A0 CS_N address (read 7:0 ] RW_N/RD_N t AVWH DS_N/WR_N (write 7:0 ] DS_N/WR_N RW_N/RD_N Fig 29. ISP1583 register access timing: multiplexed address/data bus (A0 function and Freescale mode) (1) Programmable polarity: shown as ...
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DMA timing 13.2.1 PIO mode Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. Table 108. PIO mode timing parameters CC(I/O) ...
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DIOR, DIOW (2) (write) DATA [ 7:0 ] (2) (read) DATA [ 7:0 ] (3a) HIGH READY/IORDY (3b) READY/IORDY (3c) READY/IORDY (1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0. (2) ...
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GDMA slave mode • Bits MODE[1:0] = 00: data strobes DIOR (read) and DIOW (write); see • Bits MODE[1:0] = 01: data strobes DIOR (read) and DACK (write); see • Bits MODE[1:0] = 10: data strobes DACK (read and ...
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DREQ t su3 t su1 (1) DACK (1) DIOR or DIOW (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DREQ is asserted for every transfer. Data strobes: DIOR (read), DACK (write). (1) Programmable polarity: shown as active ...
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MDMA mode Table 110. MDMA mode timing parameters CC(I/O) CC(3V3) Symbol Parameter T read/write cycle time cy1(min) t DIOR or DIOW pulse width w1(min) t data valid ...
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Application information Fig 36. Typical interface connections for generic processor mode Fig 37. Typical interface connections for split bus mode (slave mode) 15. Test information The dynamic characteristics of analog I/O ports DP and DM are determined using the ...
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In full-speed mode, an internal 1.5 kΩ pull-up resistor is connected to pin DP. Fig 38. Load impedance for the DP and DM pins (full-speed mode) ISP1583_11 Product data sheet Hi-Speed USB peripheral controller test point DUT 15 kΩ Rev. ...
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Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 0.85 mm terminal 1 index area e 1 terminal 1 64 index area ...
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TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area ball index area ...
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TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area 1 ball index area DIMENSIONS (mm are ...
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Abbreviations Table 111. Abbreviations Acronym ACK ACPI ASIC ATA ATAPI CRC DMA EMI ESR FS GDMA HS IDE MDMA MMU MO NAK NRZI NYET OTG PCB PHY PID PIE PIO PLL POR SE0 SIE SRP TTL USB ISP1583_11 Product ...
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References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB Specification Rev. 1.3 [3] Using ISP1582 composite device application with alternate settings (AN10071) [4] AT Attachment with Packet Interface Extension (ATA/ATAPI-4), ANSI INCITS ...
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Revision history Table 112. Revision history Document ID Release date ISP1583_11 20091120 • Modifications: Section 4 “Ordering • Section 5 “Marking”: updated. ISP1583_10 20090623 ISP1583_9 20090609 ISP1583_8 20090123 ISP1583_7 20080922 ISP1583_6 20070820 ISP1583_5 20070209 ISP1583-04 20050104 (9397 750 14335) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . ...
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Table 78. DMA Strobe Timing register: bit allocation . . . .58 Table 79. DMA Strobe Timing register: bit description . .58 Table 80. DMA Burst Counter register: bit allocation . . . .59 Table 81. DMA Burst Counter register: ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ISP1583BS (top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2009 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 11 — 20 November 2009 ISP1583 Hi-Speed USB peripheral controller © ST-ERICSSON 2009. All rights reserved. ...