PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet
PSD935G2-90U
Specifications of PSD935G2-90U
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PSD935G2-90U Summary of contents
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... Erase/Write Cycles of Flash Memory – 1,000 Erase/Write Cycles of PLD January 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Configurable Memory System on a Chip for 8-Bit Microcontrollers Figure 1. Packages PSD935G2 PRELIMINARY DATA TQFP80 (U) 1/3 ...
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... MCU based applications: • 4 Mbit of Flash memory • A secondary Flash memory for boot or data • Over 3,000 gates of Flash programmable logic • 64 Kbit SRAM • Reconfigurable I/O ports • Programmable power management. PSD9XX Family PSD935G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers 1 ...
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... PSD9XX Family 1.0 The PSD935G2 device offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. Introduction In-System Programming (ISP) via JTAG (Cont.) An IEEE 1149.1 compliant JTAG-ISP interface is included on the PSD enabling the entire device (both flash memories, the PLD, and all configuration rapidly programmed while soldered to the circuit board ...
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... PSD9XX into Power Down Mode. Erase/Write cycles: • Flash memory – 100,000 minimum • PLD – 1,000 minimum 3.0 PSD9XX Series Table 1. PSD9XX Product Matrix Part # PSD9XX I/O Series Device Pins Inputs Macrocells Macrocells Outputs PSD935G2 52 PSD9XX PSD913G2 27 PSD934F2 27 PLD Input Output PLD ...
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PLD INPUT BUS PAGE REGISTER CNTL0, CNTL1, PROG. CNTL2 MCU BUS INTRF AD0 – AD15 ADIO PORT 66 PROG. PORT PF0 – PF7 PORT F PROG. PORT PG0 – PG7 PORT G * Additional address lines can be ...
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... There is a slight penalty to PLD propagation time when invoking the non-Turbo bit. 4.3 I/O Ports The PSD935G2 has 52 I/O pins divided among seven ports (Port and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed address/data busses ...
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... The APD unit has a Power Down Mode that helps reduce power consumption. The PSD935G2 also has some bits that are configured at run-time by the MCU to reduce power consumption of the GPLD. The turbo bit in the PMMR0 register can be turned off and the GPLD will latch its outputs and go to standby until the next transition on its inputs. ...
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... PSD935G2 5.0 The PSD9XX series is supported by PSDsoft a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and click Development environment. The designer does not need to enter Hardware Definition Language (HDL) System equations (unless desired) to define PSD pin functions and memory map information. The general design flow is shown in Figure 2 below ...
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... PSD9XX Family 6.0 The following table describes the pin names and pin functions of the PSD935G2. Pins that have multiple names and/or functions are defined using PSD Configuration. Table 5. PSD935G2 Pin Descriptions Pin Name ADIO0-7 ADIO8-15 CNTL0 CNTL1 CNTL2 Reset 8 Pin* (TQFP Pkg ...
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... PSD935G2 Table 5. PSD935G2 Pin Pin Name Pkg.) Descriptions PA0-PA7 51-58 (cont.) PB0-PB7 61-68 PC0-PC7 41-48 PD0 PD1 PD2 PD3 PE0 PE1 PE2 Pin* (TQFP Type I/O Port A, PA0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port Drain 2 ...
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... As address A0-3 inputs in 80C51XA mode 5. As data bus port (D0-7) in non-multiplexed bus configuration I/O Port G, PG0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address outputs. 8,30, 49,50, 70 9,29, 69 PSD935G2 Description ...
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... PSD935G2 7.0 PSD935G2 Table 6 shows the offset addresses to the PSD935G2 registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the Register internal PSD935G2 registers. Table 6 provides brief descriptions of the registers in CSIOP Description and space ...
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... PSD9XX Family 8.0 All the registers in the PSD935G2 are included here for reference. Detail description of the registers are found in the Functional Block section of the Data Sheet. Register Bit Definition Data In Registers – Port and G Bit 7 Port Pin 7 Bit definitions: Read only registers, read Port pin status when Port is in MCU I/O input Mode. ...
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... PSD935G2 Flash Boot Protection Register 8.0 Register Bit Bit 7 Definition Security_Bit (cont.) Bit definitions: Sec<i>_Prot Sec<i>_Prot Security_Bit Page Register Bit 7 Pgr7 Bit definitions: Configure Page input to PLD. Default Pgr[7:0] = 00. PMMR0 Register Bit Not used bit should be set to zero. Bit definitions: (default is 0) Bit Automatic Power Down (APD) is disabled ...
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... B_type[1:0] = 0h, Boot block is Flash memory. 14 Bit 6 Bit 5 Bit 4 FL_data * * Bit 6 Bit 5 Bit 4 S_size 2 S_size 1 S_size 0 Bit 6 Bit 5 Bit 4 B_type 1 B_type 0 * PSD935G2 Bit 3 Bit 2 Bit 1 Boot_data FL_code Boot_code SR_code Bit 3 Bit 2 Bit 1 F_size 3 F_size 2 F_size 1 Bit 3 Bit 2 Bit 1 B_size 3 B_size 2 B_size 1 Bit 0 ...
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... PE4. This pin is set up using PSDsoft. 9.1.1.1 Memory Block Selects The decode PLD in the PSD935G2 generates the chip selects for all the internal memory blocks (refer to the PLD section). Each of the eight Flash memory sectors have a Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the four Secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can contain up to three product terms ...
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... FA15 to a particular Flash sector only. 9.1.1.3 The Ready/Busy Pin (PE4) Pin PE4 can be used to output the Ready/Busy status of the PSD935G2. The output on the pin will be a ‘0’ (Busy) when Flash memory blocks are being written to, or when the Flash memory block is being erased. The output will be a ‘ ...
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... Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). The PSD935G2 main Flash and secondary Flash support these instructions (see Table 8): Erase memory by chip or sector Suspend or resume sector erase ...
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... F0 @ any address 1 AAh 55h 20h @555h @AAAh @555h 1 A0h PD@PA @xxxh 1 90h 00h @xxxh @xxxh PSD935G2 Cycle 4 Cycle5 Cycle 6 Cycle 7 “Read” ID @x01h “Read” 00h or 01h @x02h PD@PA AAh 55h 30h 30h @555h @AAAh @SA @next SA (Note 7) AAh 55h ...
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... The 9.1.1.5 Power-Up Condition PSD935G2 The PSD935G2 internal logic is reset upon power-up to the read array mode. The FSi and CSBOOTi select signals, along with the write strobe signal, must be in the false state Functional during power-up for maximum security of the data contents and to remove the possibility of Blocks data being written on the first edge of a write strobe signal ...
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... Toggle Flag DQ6 The PSD935G2 offers another way for determining when the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or CSBOOTi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to read any byte of the memory ...
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... Figure 4 shows the Data Polling algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD935G2 begins. The MCU then reads the location of the word to be programmed in Flash to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the original data word to be programmed ...
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... When the MCU issues a programming instruction, the embedded algorithm within the PSD935G2 begins. The MCU then reads the location to be programmed in Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling (two consecutive reads yield the same value), and the Error bit on DQ5 remains ‘ ...
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... PSD935G2 The 9.1.1.7.2 Data Toggle PSD935G2 It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to Flash with Functional the word that was intended to be written. Blocks When using the Data Toggle method after an erase instructin, Figure 5 still applies. DQ6 (cont.) will toggle until the erase operation is complete. A ‘ ...
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... Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode not necessary to program the Flash sector with 00h as the PSD935G2 will do this automatically before erasing. ...
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... An Erase Suspend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD935G2 internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. ...
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... Bit Flash Boot Sector <i> is write protected Flash Boot Sector <i> is not write protected Security Bit in device has not been set Security Bit in device has been set. PSD935G2 Bit 3 Bit 2 Bit 1 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Bit 3 Bit 2 Bit 1 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot ...
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... Vstby pin (PE6). If you have an external battery connected to the PSD935G2, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains greater. If the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs ...
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... The 80C51 and compatible family of microcontrollers, can be configured to have separate address spaces for code memory (selected using PSEN) and data memory (selected using RD). Any of the memories within the PSD935G2 can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the PSD’s CSIOP space ...
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... PSD935G2 The 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces PSD935G2 9.1.3.2.1 Separate Space Modes Functional Code memory space is separated from data memory space. For example, the PSEN Blocks signal is used to access the program code from the main Flash Memory, while the RD signal is used to access data from the secondary Flash memory, SRAM and I/O Ports ...
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... D0-D7. The microcontroller can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 9. Page Register 30 RESET PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 PGR7 R/W PAGE REGISTER PSD935G2 INTERNAL SELECTS AND LOGIC DPLD AND GPLD FLASH PLD ...
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... PSD935G2 The 9.1.5 Memory ID Registers PSD935G2 The 8-bit read only memory status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 Functional and Memory ID1 registers. The content of the registers are defined as follow: ...
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... NOTE: The address inputs are A[19:4] in 80C51XA mode. The Turbo Bit The PLDs in the PSD935G2 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing ...
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... PSD935G2 Figure 10. PLD Block Diagram 8 DATA BUS 66 GENERAL PURPOSE PLD 66 PAGE REGISTER 8 DECODE PLD GPLD PLD OUT 8 PLD OUT 8 PLD OUT 8 PORT A PLD INPUT 8 PORT B PLD INPUT 8 PORT C PLD INPUT 8 PORT D PLD INPUT 4 PORT F PLD INPUT 8 PSD9XX Family FLASH MEMORY SELECTS ...
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... PT expansion). For optimum results, choose a GPLD output pin with a large number of native PTs for complicated logic. Table 13: GPLD Product Term Availability GPLD Output on Port Pin Port A, pins PA0-3 Port A, pins PA4-7 Port B, pins PB0-3 Port B, pins PB4-7 Port C, pins PC0-7 34 Number of Native Product Terms PSD935G2 ...
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I /O PORTS (PORT A,B,C,F) (32) PGR0 -PGR7 (16 15 3:0 ] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL [ 2 READ/WRITE CONTROL SIGNALS) RESET RD_BSY * NOTES: 1. The address inputs are ...
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... PSD9XX Family Figure 12. The Micro Cell and I/O Port 36 BUS INPUT PLD PSD935G2 ...
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... Figure 14 shows an example of a system using a microcontroller with a 8-bit non-multiplexed bus and a PSD935G2. The address bus is connected to the ADIO Port, and the data bus is connected to Port F. Port tri-state mode when the PSD935G2 is not accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports may be used for additional address inputs ...
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... D [ 7:0 ] MICRO 15 BHE ALE PSD935G2 PSD935G2 PORT F ADIO PORT PORT CNTRL0 ) RD ( CNTRL1 ) PORT BHE ( CNTRL2 ) A, RST ALE ( PD0 ) PORT D PSD935G2 D [ 7:0 ] PORT F ADIO PORT PORT CNTRL0 ) RD ( CNTRL1 ) PORT BHE ( CNTRL2 ) A,B or RST C ALE ( PD0 ) PORT OPTIONAL ) OPTIONAL ) A [ 23: OPTIONAL ) A [ 23:16 ] ...
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... Figure 15. Configurations 2 and 3 have the same bus connection as shown in Figure 16. There is only one read input (PSEN) connected to the Cntl1 pin on the PSD935G2. The A16 connection to the PA0 pin allows for a larger address input to the PSD935G2. Configuration 4 is shown in Figure 17. The RD signal is connected to Cntl1 and the PSEN signal is connected to the CNTL2 ...
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... Burst Mode is identical to the normal bus cycle, except the address setup and hold time with respect to ALE does not apply. 9.3.3.4 68HC11 Figure 19 shows an interface to a 68HC11 where the PSD935G2 is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR signals for external devices. ...
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... PSD935G2 Figure 15. Interfacing the PSD935G2 with an 80C31 19 X1 CRYSTAL RESET RESET 12 INT0 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 P1.7 10 RXD 11 TXD 31 EA/VP 80C31 RESET 39 AD0 P0.0 38 AD1 P0.1 37 AD2 P0.2 36 AD3 P0.3 35 AD4 P0.4 34 AD5 P0.5 33 AD6 P0.6 32 AD7 P0 ...
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... PSD9XX Family Figure 16. Interfacing the PSD935G2 to the 80C251, with One Read Input U1 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 CRYSTAL P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 10 RESET RESET 35 EA 80C251SB RESET RESET **Connection is optional. **Non-page mode: AD[7:0] - ADIO[7:0]. 42 A17 ...
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... PSD935G2 Figure 17. Interfacing the PSD935G2 to the 80C251, with Read and PSEN Inputs 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 CRYSTAL P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 10 RESET RESET 35 EA 80C251SB RESET RESET P0.7 24 AD8 13 P2.0 25 AD9 14 P2.1 ...
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... PSD9XX Family Figure 18. Interfacing the PSD935G2 to the 80C51XA, 8-Bit Data Bus 21 XTAL1 CRYSTAL 20 XTAL2 11 RXD0 13 TXD0 6 RXD1 7 TXD1 9 T2EX RESET 10 RST 14 INT0 15 INT1 EA/WAIT 17 BUSW XA-G3 RESET 44 43 A4D0 A4D0 42 A5D1 A5D1 41 A6D2 A6D2 40 A7D3 A7D3 39 A8D4 A8D4 38 A9D5 A9D5 37 A10D6 ...
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... PSD935G2 Figure 19. Interfacing the PSD935G2 with a 68HC11 34 PA0 33 PA1 32 PA2 31 PA3 30 PA4 29 PA5 28 PA6 27 PA7 8 XT CRYSTAL IRQ 18 XIRQ 20 PD0 21 PD1 22 PD2 23 PD3 24 PD4 25 PD5 43 PE0 45 PE1 47 PE2 RESET 49 PE3 44 PE4 46 PE5 48 PE6 50 PE7 52 VRH 51 VRL 2 MODB 3 MODA 68HC11E9 RESET RESET ...
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... All other modes can be changed by the microcontroller at run-time. Table 16 summarizes which modes are available on each port. Table 19 shows how and where the different modes are configured. Each of the port operating modes are described in the following subsections. 46 PSD935G2 ...
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... PSD935G2 The Table 16. Port Operating Modes PSD935G2 Port Mode Functional MCU I/O Blocks PLD Outputs (cont.) PLD Inputs Address Out Address In Data Port JTAG ISP Figure 20. General I/O Port Architecture PSD9XX Family Port A Port B Port C Port D Yes Yes Yes Yes Yes ...
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... MCU I/O Mode In the MCU I/O Mode, the microcontroller uses the PSD935G2 ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD935G2 are mapped into the microcontroller address space. The addresses of the ports are listed in Table 6. ...
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... PSD935G2 The 9.4.2.3 Address Out Mode PSD935G2 For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external Functional devices. Either the output enable or the corresponding bits of both the Direction Register Blocks and Control Register must be set to a ‘ ...
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... Direction Register for Port D has only the four least significant bits active. Table 20. Port Pin Direction Control Direction Register Bit Table 21. Port Direction Assignment Example Bit Port MCU Access E,F,G Write/Read A,B,C,D,E,F,G Write/Read A,B,C,D,E,F,G Write/Read Port Pin Mode 0 Input 1 Output Bit 6 Bit 5 Bit PSD935G2 Bit 3 Bit 2 Bit Bit 0 1 ...
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... PSD935G2 The 9.4.3.3 Drive Select Register PSD935G2 The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should Functional be used for pins configured as Open Drain. ...
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... Figure 21 Port A, B and C 52 – Input to the PLDs. pins PA[7:0] and PB[7:0] can be configured to Open Drain Mode. DATA OUT REG. DATA OUT GPLD OUTPUT READ MUX P D DATA IN B DIR REG PLD INPUT PSD935G2 PORT PIN OUTPUT MUX OUTPUT SELECT ...
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... Port E can be configured to perform one or more of the following functions (see Figure 23): MCU I/O Mode In-System Programming – JTAG port can be enabled for programming/erase of the PSD935G2 device. (See Section 9.6 for more information on JTAG programming.) Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O functions. ...
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... Open Drain – pins can be configured in Open Drain Mode Figure 23. Ports E, F and G Structure 54 DATA OUT REG ADDRESS 7 15:8 ] ALE G READ MUX CONTROL REG DIR REG ISP OR BATTERY BACK-UP (PORT E) PSD935G2 DATA OUT ADDRESS OUTPUT MUX OUTPUT SELECT DATA IN PLD INPUT (PORT F) PORT PIN CONFIGURATION BIT ...
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... ALE and WRH/DBE) if none of these signals are used in PLD logic equations. The PSD935G2 devices have a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current) ...
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... Table 24. Power Down Mode’s Effect on Port Function MCU I/O PLD Out Address Out Data Port Peripheral I/O Table 25. PSD935G2 Timing and Standby Current During Power Mode Power Down NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this 56 Ports Pin Level ...
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... PSD935G2 The Figure 24. APD Logic Block PSD935G2 Functional Blocks APD EN PMMR0 BIT 1=1 (cont.) ALE RESET CSI CLKIN Figure 25. Enable Power Down Flow Chart TRANSITION DETECTION CLR PD APD COUNTER EDGE PD DETECT DISABLE MAIN AND SECONDARY FLASH/SRAM RESET Enable APD Set PMMR0 Bit ...
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... Every CLKIN change will power up the PLD when Turbo bit is off. Bit 6 Bit 5 Bit 4 ** PLD PLD PLD array array array DBE ALE CNTL2 1 = off 1 = off 1 = off Note: In 80C51XA mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0]. PSD935G2 Bit 3 Bit 2 Bit 1 PLD APD * Turbo Enable 1 = off Bit 3 Bit 2 Bit PLD PLD ...
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... Input Clock The PSD935G2 provides the option to turn off the CLKIN input to the PLD AND array to save AC power consumption. During Power Down Mode, or, if the CLKIN input is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be disconnected from the PLD AND array by setting bit “ ...
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... PSD935G2 remains in the reset state for an additional tOPR (maximum 120 ns) nanoseconds before the first memory access is allowed. The PSD935G2 Flash memory is reset to the read array mode upon power up. The FSi and CSBOOTi select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal ...
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... Programming In-Circuit using the JTAG-ISP Interface The JTAG-ISP interface on the PSD935G2 can be enabled on Port E (see Table 29). All memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be programmed through the JTAG-ISC interface. A blank part can be mounted on a printed circuit board and programmed using JTAG-ISP ...
Page 63
... TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.3. TSTAT will be high when the PSD935G2 device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Secondary Flash Block. ...
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... PSD935G2 10.0 Symbol Absolute T STG Maximum Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended ...
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... Figures 27 and 27a show the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo bit is "OFF". Figure 27. PLD I CC /FrequencyConsumption 64 110 100 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) PSD935G2 Beta Information ( ± 10%) PT 100 ...
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... PSD935G2 AC/DC Figure 27a. PLD I Parameters (cont.) Example of PSD935G2 Typical Power Calculation at V Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used ...
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... Freq ALE + % PLD x (from graph using Freq PLD µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA µ 0 µA + 0 µ mA. PSD935G2 = 5 Turbo Off Mode MHz = 4 MHz = 80 (no additional power above base) = 10 45/176 = 25 ...
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... PSD935G2 PSD935G2 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V V Min for Flash Erase and Program ...
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... B – Vstby Output M – Output Micro Cell Signal Behavior – Pulse Width 68 t – Time from Address Valid to ALE Invalid. AVLX – Time – Logic Level Low or ALE – Logic Level High – Valid – No Longer a Valid Logic Level – Float PSD935G2 ...
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... NOTES timing has the same timing as DS and PSEN signals and PSEN have the same timing. 3. Any input used to select an internal PSD935G2 function multiplexed mode, latched addresses generated from ADIO delay to address output on any Port timing has the same timing as DS signals. ...
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... WHPV Valid Using I/O Port Data Register Address Input Valid to Address t AVPV Output Delay NOTES: 1. Any input used to select an internal PSD935G2 function multiplexed mode, latched addresses generated from ADIO delay to address output on any Port timing has the same timing signals Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. ...
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... PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (5V ± 10% Versions) Power Down Timing (5 V ± 10%) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t to Internal PDN Valid Signal CLWH NOTE the CLKIN clock period. CLCL V Timing (5 V ± ...
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... PSD9XX Family Microcontroller Interface – PSD935G2 AC/DC Parameters (5V ± 10% Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t Sector Erase (Preprogrammed to 00) WHQV3 t Sector Erase WHQV2 t Word Program WHQV1 Program/Erase Cycles (Per Sector) ...
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... PSD935G2 PSD935G2 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V V Min for Flash Erase and Program ...
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... W – Internal PDN Signal B – Vstby Output Signal Behavior – Pulse Width 74 t – Time from Address Valid to ALE Invalid. AVLX – Time – Logic Level Low or ALE – Logic Level High – Valid – No Longer a Valid Logic Level – Float PSD935G2 ...
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... PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Read Timing (3 3.6 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data Valid ...
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... Address Input Valid to Address t AVPV Output Delay NOTES: 1. Any input used to select an internal PSD935G2 function multiplexed mode, latched addresses generated from ADIO delay to address output on any Port timing has the same timing signals Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory. ...
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... PSD935G2 Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Power Down Timing (3 3.6 V Versions) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t CLWH to Internal PDN Valid Signal NOTE the CLKIN clock period. CLCL V Timing (3 3.6 V Versions) ...
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... PSD9XX Family Microcontroller Interface – PSD935G2 AC/DC Parameters (3 3.6 V Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t Sector Erase (Preprogrammed to 00) WHQV3 t Sector Erase WHQV2 t Word Program WHQV1 Program/Erase Cycles (Per Sector) ...
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... PSD935G2 Figure 28. Read Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV * t and t are not required 80C51XA in Burst Mode. AVLX LXAX * t AVLX t LXAX t LVLX ADDRESS VALID t AVQV ADDRESS VALID t SLQV t RLQV t RLRH t THEH ADDRESS OUT PSD9XX Family ...
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... A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ADDRESS OUT PSD935G2 DATA VALID DATA VALID t DVWH t WHDX t WHAX t EHEL t ELTL t WLMV t WHPV STANDARD MCU I/O OUT ...
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... PSD935G2 Figure 30. Combinatorial Timing – PLD GPLD INPUT GPLD OUTPUT Figure 31. JTAG-ISP Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO ISCCH t ISCCL t t ISCPSU ISCPH PSD9XX Family t ISCPZV t ISCPCO t ISCPVZ 81 ...
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... Figure 33. Key to Switching Waveforms WAVEFORMS 82 t NLNH– OPR POWER ON RESET INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM DON'T CARE OUTPUTS ONLY PSD935G2 t NLNH t NLNH-A t OPR WARM RESET OUTPUTS STEADY OUTPUT WILL BE CHANGING FROM WILL BE CHANGING CHANGING, STATE UNKNOWN ...
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... AC Testing Load Circuit 17.0 Upon delivery from ST, the PSD935G2 device has all bits in the PLDs and memories in the “1” or high state. The configuration bits are in the “0” or low state. The Programming code, configuration, and PLDs logic are loaded through the procedure of programming. ...
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... PG7 GND 70 PF0 71 PF1 72 PF2 73 PF3 74 PF4 75 PF5 76 PF6 77 PF7 78 RESET 79 CNTL2 80 PSD935G2 Pin Assignments PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 CNTL1 PB0 PB1 PB2 PB3 PB4 PB5 ...
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... PSD935G2 19.0 Figure 36. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) PSD935G2 Package Information PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND V CC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 (Package Type PSD9XX Family 60 CNTL1 59 CNTL0 58 PA7 ...
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... A Load Coplanarity: e1 Millimeters Max Notes 7° 1.20 1.05 0.27 Reference 0.20 14.05 12.05 Reference 14.05 12.05 Reference Reference 0.75 PSD935G2 Standoff: 0.05 mm Min. L 0.102 mm Max. Inches Min Max 0° 8° – 0.047 0.037 0.041 0.007 0.011 0.008 0.512 0.551 0.433 0.472 ...
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... Selector Guide – PSD935G2 Series Part # MCU PLDs/Decoders 5 Data Inputs Input Macrocells Path Volts Output Macrocells Outputs Page Reg. PSD935G2 8 52 – – 24 8-bit PSD913F2 8 27 – 8-bit PSD934F2 8 27 – 8-bit I/O Memory Other Ports Flash Program Store ISP via JTAG ...
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... SRAM SIZE 0 = 0Kb 1 = 16Kb 2 = 32Kb 3 = 64Kb NVM SIZE 1 = 256Kb 2 = 512Kb 3 = 1Mb 4 = 2Mb 5 = 4Mb I/O COUNT & OTHER I I/O 2ND NVM TYPE, SIZE & CONFIGURATION 1 = EEPROM, 256Kb 2 = FLASH, 256Kb 2nd Array 22.0 Ordering Information Part Number PSD935G2-70U PSD935G2-90U PSD935G2-90UI PSD935G2V-90U PSD935G2V-12U PSD935G2V-12UI ...
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... Min from changed tDVWH -70 Min from 12 to 25, changed tWLWH -70 Min from 25 to 28. PSD935G2: Configurable Memory System on a Chip for 8-Bit Microcontrollers Front page, and back two pages format, added to the PDF file 31-Jan-2002 1.2 References to Waferscale, WSI, EasyFLASH and PSDsoft 2000 ...
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... All other names are the property of their respective owners STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © 2002 STMicroelectronics - All Rights Reserved www.st.com PSD935G2 3/3 ...