ISP1581BD STEricsson, ISP1581BD Datasheet
ISP1581BD
Specifications of ISP1581BD
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ISP1581BD Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - Philips ...
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General description The ISP1581 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus (USB) peripheral controller, which fully complies with the Universal Serial Bus Specification Rev. 2 provides high-speed USB communication capacity to systems based on a ...
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... Ordering information Table 1: Ordering information Type number Package Name ISP1581BD LQFP64 9397 750 13462 Product data Direct interface to ATA/ATAPI peripherals; applicable only in the split bus mode Complies fully with Universal Serial Bus Specification Rev. 2.0 Complies with most Device Class specifications High performance USB peripheral controller with integrated Serial Interface Engine (SIE), PIE, FIFO memory, data transceiver and 3 ...
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USB 3.3 V 1.5 k SoftConnect RPU 7 RREF 8 Hi-Speed USB TRANSCEIVER 12 POWER-ON internal RESET reset RESET 3.3 V digital supply 2 VOLTAGE V CC(5.0) REGULATORS CONTROLLER 3.3 V analog 5 ...
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... RPU 7 RREF 8 MODE1 9 RESET 10 EOT 11 DREQ 12 DACK 13 DIOR 14 DIOW 15 INTRQ 16 Rev. 06 — 23 December 2004 ISP1581 Hi-Speed USB peripheral controller ISP1581BD © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 48 DATA6 47 DATA5 46 DATA4 45 DATA3 44 DATA2 43 V CC(3.3) 42 DGND 41 DATA1 40 DATA0 AD7 39 38 ...
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Philips Semiconductors 6.2 Pin description Table 2: Symbol DGND V CC(5.0) AGND V CCA(3. RPU RREF MODE1 RESET EOT DREQ DACK 9397 750 13462 Product data Pin description for LQFP64 [1] [2] Pin Type Description 1 - digital ...
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Philips Semiconductors Table 2: Symbol DIOR DIOW INTRQ CS1 CS0 BUS_CONF/ DA0 MODE0 DA1 DA2 9397 750 13462 Product data Pin description for LQFP64 [1] [2] Pin Type Description 14 I/O DMA read strobe (programmable polarity); direction depends on bit ...
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Philips Semiconductors Table 2: Symbol READY/ IORDY DGND V CC(3.3) CS (R/W)/RD DS/WR INT ALE/A0 AD0 9397 750 13462 Product data Pin description for LQFP64 [1] [2] Pin Type Description 22 I/O Generic processor mode: ready signal (READY; output) A ...
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Philips Semiconductors Table 2: Symbol AD1 AD2 AD3 AD4 AD5 DGND V CC(3.3) AD6 AD7 DATA0 DATA1 DGND V CC(3.3) DATA2 DATA3 9397 750 13462 Product data Pin description for LQFP64 [1] [2] Pin Type Description 31 I/O bit 1 ...
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Philips Semiconductors Table 2: Symbol DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 V CC(3.3) XTAL2 XTAL1 9397 750 13462 Product data Pin description for LQFP64 [1] [2] Pin Type Description 46 I/O bit 4 of ...
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Philips Semiconductors Table 2: Symbol DGND WAKEUP TEST V CC(3.3) [1] [2] [3] [4] [5] 9397 750 13462 Product data Pin description for LQFP64 [1] [2] Pin Type Description 61 - digital ground 62 I wake-up input (edge triggered); a ...
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Philips Semiconductors 7. Functional description The ISP1581 is a high-speed USB device controller. It implements the Hi-Speed USB and Original USB physical layer, the packet protocol layer and maintains USB endpoints concurrently (control IN and control OUT, ...
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Philips Semiconductors 7.1 Hi-Speed USB transceiver The analog transceiver interfaces directly to the USB cable via integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 k between pin RREF and ground to ensure an accurate current mirror that ...
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Philips Semiconductors 7.4 Voltage regulators Two 5 V-to-3.3 V voltage regulators are integrated on-chip to separately supply the analog transceiver and the internal logic. The output of these voltage regulators are termed as V block and the digital block, respectively. ...
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Philips Semiconductors 7.8 DMA Interface and DMA Handler The DMA block can be subdivided into two blocks: the DMA Handler and the DMA Interface. The firmware writes to the DMA Command register to start a DMA transfer (see Table UDMA ...
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Philips Semiconductors Figure 4 Fig 4. 9397 750 13462 Product data shows the availability of the clock with respect to the external POR. POR EXTERNAL CLOCK Stable external clock available at A. Clock with respect to the ...
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Philips Semiconductors 8. Modes of operation The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at power-up: • • Details of the bus configurations for each mode are given in circuits for each mode are given in Table ...
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Philips Semiconductors Table 4: Register overview …continued Name Destination DMA registers DMA Command DMA controller DMA Transfer Counter DMA controller DMA Configuration DMA controller DMA Hardware DMA controller 1F0 Task File ATAPI peripheral 1F1Task File ATAPI peripheral 1F2 Task File ...
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Philips Semiconductors 9.1 Register access Register access depends on the bus width used: • • Endpoint specific registers are indexed via the Endpoint Index register. The target endpoint must be selected first, before accessing the following registers: • • • ...
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Philips Semiconductors 9.2.2 Mode register (address: 0CH) This register consists of 1 byte (bit allocation: see upper byte is ignored. The Mode register controls the resume, suspend and wake-up behavior, interrupt activity, soft reset, clock signals and SoftConnect operation. Table ...
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Philips Semiconductors • The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow the user to individually configure when the ISP1581 will send an interrupt to the external microprocessor. Bit INTPOL controls the signal polarity of the INT output (active ...
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Philips Semiconductors All data IN transactions use the Transmit buffers (TX), which are handled by the DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 ...
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Philips Semiconductors Table 13: Bit 9.2.5 DMA Configuration register (address: 38H) See 9.2.6 DMA Hardware register (address: 3CH) See 9.3 Data flow registers 9.3.1 Endpoint Index register (address: 2CH) The Endpoint Index register ...
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Philips Semiconductors Table 15: Bit Table 16: Buffer name SETUP Data OUT Data IN 9.3.2 Control Function register (address: 28H) The Control Function register is used to perform the buffer management on ...
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Philips Semiconductors Table 18: Bit 9.3.3 Data Port register (address: 20H) This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed endpoint. In case of an 8-bit ...
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Philips Semiconductors Remark: The buffer can be validated or cleared automatically by using the Buffer Length register (see Table 19: Data Port register: bit allocation Bit 15 Symbol Reset Bus reset Access Bit 7 Symbol Reset Bus reset Access Table ...
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Philips Semiconductors Table 21: Buffer Length register: bit allocation Bit 15 Symbol Reset Bus reset Access Bit 7 Symbol Reset Bus reset Access 9.3.5 Endpoint MaxPacketSize register (address: 04H) This register determines the maximum packet size for all endpoints except ...
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Philips Semiconductors 9.3.6 Endpoint Type register (address: 08H) This register sets the Endpoint type of the indexed endpoint: isochronous, bulk or interrupt. It also serves to enable the endpoint and configure it for double buffering. Automatic generation of an empty ...
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Philips Semiconductors 9.4 DMA registers Two types of Generic DMA transfer and three types of IDE-specified transfer can be done by writing the proper opcode in the DMA Command Register. The control bits are given in GDMA read/write (opcode = ...
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Philips Semiconductors UDMA read/write (opcode = 02H/03H) — Ultra DMA mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev Pins DA0 to DA2, CS0 and CS1 are used to select ...
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Philips Semiconductors Table 27: Control bits DMA Hardware register (see MASTER MDMA read/write (opcode = 06H/07H) DMA Configuration register (see DMA_MODE[1:0] ATA_MODE DMA Hardware register (see MASTER UDMA read/write (opcode = 02H/03H) DMA Configuration register (see DMA_MODE[1:0] IGNORE_IORDY ATA_MODE DMA ...
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Philips Semiconductors Table 30: Code (Hex) Name 9397 750 13462 Product data DMA commands Description 00 GDMA Read Generic DMA IN token transfer (slave mode only): Data is transferred from the external DMA bus to the internal buffer. Strobe: DIOW ...
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Philips Semiconductors Table 30: Code (Hex) Name [1] 9.4.2 DMA Transfer Counter register (address: 34H) This 4-byte register is used to set up the total byte count of a DMA transfer (DMACR). It indicates the remaining number of bytes left ...
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Philips Semiconductors Bit 15 Symbol Reset Bus reset Access Bit 7 Symbol Reset Bus reset Access Table 32: Bit 9.4.3 DMA Configuration register (address: 38H) This register defines ...
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Philips Semiconductors Table 34: Bit DMA_MODE[1: 9397 750 13462 Product data DMA Configuration register: bit description [1] Symbol Description - reserved IGNORE_IORDY A logic 1 ignores the ...
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Philips Semiconductors Table 34: Bit [1] [2] [3] [4] 9.4.4 DMA Hardware register (address: 3CH) The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table This register determines the polarity ...
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Philips Semiconductors Table 36: Bit 9.4.5 DMA Strobe Timing register (address: 60H) This 1-byte register controls the strobe timings for the MDMA mode, when the DMA_MODE bits in the DMA Configuration ...
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Philips Semiconductors Table 37: DMA Strobe Timing register: bit allocation Bit 7 Symbol reserved Reset - Bus reset - Access R/W R/W Table 38: Bit [1] Fig 5. Programmable strobe timing. 9.4.6 Task File ...
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Philips Semiconductors Table 40: Task file 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 3F6 3F7 In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read accesses before the proper PIO write/read is generated on the ...
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Philips Semiconductors Table 44: Task File register 1F3 (address: 4AH): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = H. Bit 7 Symbol Reset Bus reset Access Table 45: Task File register 1F4 ...
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Philips Semiconductors Table 49: Task File register 3F6 (address: 4EH): bit allocation CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L. Bit 7 Symbol Reset Bus reset Access Table 50: Task File register 3F7 ...
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Philips Semiconductors Table 52: Bit Table 53: INT_EOT [1] 9.4.8 DMA Interrupt Enable register (address: 54H) This 2-byte register controls the interrupt generation of the source bits ...
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Philips Semiconductors Bit 7 Symbol IE_1F0_ IE_1F0_ WF_E WF_F Reset 0 Bus reset 0 Access R/W R/W 9.4.9 DMA Endpoint register (address: 58H) This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA transfers. The ...
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Philips Semiconductors Table 57: Interrupt register: bit allocation Bit 31 Symbol Reset - Bus reset - Access R/W R/W Bit 23 Symbol EP6TX EP6RX Reset 0 Bus reset 0 Access R/W R/W Bit 15 Symbol EP2TX EP2RX Reset 0 Bus ...
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Philips Semiconductors Table 58: Bit 9.5.2 Chip ID register (address: 70H) This read-only register contains the chip identification and the hardware version numbers. The firmware should check this information to ...
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Philips Semiconductors Table 60: Bit 9.5.3 Frame Number register (address: 74H) This read-only register contains the frame number of the last successfully received Start Of Frame (SOF). The register contains 2 ...
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Philips Semiconductors Table 64: Bit 9.5.5 Test Mode register (address: 84H) This 1-byte register allows the firmware to set the ( states for testing purposes. The bit allocation is given in Remark: ...
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Philips Semiconductors ISP1581 V CC(5. CCA(3. CC(3. CC(3. CC(3. CC(3. CC(3. µF 0.01 µF Fig 6. ISP1581 with 5.0 V supply. ISP1581 V CC(5. ...
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Philips Semiconductors 11. Limiting values Table 67: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current lu V electrostatic discharge voltage esd T ...
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Philips Semiconductors Table 70: Static characteristics: digital pins V = 4 GND Symbol Parameter Input levels V LOW-level input voltage IL V HIGH-level input voltage IH Output levels V LOW-level output ...
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Philips Semiconductors Table 71: Static characteristics: analog I/O pins ( 4 GND Symbol Parameter V high-speed HIGH-level output HSOH voltage (differential) V chirp-J output voltage CHIRPJ ...
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Philips Semiconductors Table 73: Dynamic characteristics: analog I/O pins ( 4 GND amb Symbol Parameter V output signal crossover voltage CRS High-speed mode t high-speed differential ...
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Philips Semiconductors T PERIOD 3.3 V differential data lines the bit duration corresponding with the USB data rate. PERIOD Fig 9. Receiver differential data jitter. Fig 10. Receiver SE0 width tolerance. 9397 750 13462 Product data ...
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Philips Semiconductors 14.1 Register access timing 14.1.1 Generic Processor mode (BUS_CONF = 7:0 ] (read) DATA [ 15 (write) DATA [ 15 (I2) Fig 11. ISP1581 register access timing: separate address and ...
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Philips Semiconductors RD/WR CS READY Fig 13. ISP1581 READY signal timing. Table 74: ISP1581 register access timing parameters: separate address and data buses V = 4 GND amb Symbol Parameter Reading ...
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Philips Semiconductors 14.1.2 Split Bus mode (BUS_CONF = 0) Split Bus mode (BUS_CONF = 0, MODE1 = 0, MODE0 = 0/1) CS (read 7:0 ] (write 7 (I2) R/W (I1) ALE Fig 14. ISP1581 ...
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Philips Semiconductors CS ALE WR RD Fig 16. Set-up and hold time. Table 75: ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 4 GND amb Symbol ...
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Philips Semiconductors Split Bus mode (BUS_CONF = 0, MODE1 = 1, MODE 0 = 0/1) t A0WL A0 CS (read 7 AVWH WR (write 7 (I2) RD (I1) Fig 17. ISP1581 ...
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Philips Semiconductors t A0WL A0 CS (read 7:0 ] R/W t AVWH DS (write 7 (I2) R/W (I1) Fig 18. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 ...
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Philips Semiconductors t A0WL A0 CS (read 7 AVWH WR (write 7 (I2) RD (I1) Fig 19. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 ...
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Philips Semiconductors 14.2 DMA timing 14.2.1 PIO mode (1) device address valid (4) DIOR, DIOW (2) (write) DATA [ 7:0 ] (2) (read) DATA [ 7:0 ] HIGH (3a) IORDY (3b) IORDY (3c) IORDY (1) The device address consists of ...
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Philips Semiconductors Table 77: PIO mode timing parameters V = 4 GND amb Symbol Parameter t data set-up time before DIOR on su3(min) (minimum) t data hold time after DIOR off ...
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Philips Semiconductors (2) DREQ t su1 (1) DACK HIGH (1) DIOR/DIOW (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobe: DACK (read/write). ...
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Philips Semiconductors (2) DREQ t su1 (1) DACK HIGH (1) DIOR/DIOW (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DREQ is asserted for every transfer. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable ...
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Philips Semiconductors (2) DREQ t su1 (1) DACK HIGH (1) DIOR/DIOW (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here ...
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Philips Semiconductors Table 78 Symbol T cy1 t su1 su2 t su3 t a1 14.2.3 MDMA mode (2) DREQ (1) DACK t su1 ...
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Philips Semiconductors Table 79 Symbol t su2(min) t h2(min) t su1(min) t h1(min) t w2(min) t d2(max) t d3(max) [1] 14.2.4 UDMA mode (1) DIOR (sender) (1) DATA [ 15:0 ] (sender) (1) IORDY (receiver) (1) DATA [ ...
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Philips Semiconductors DREQ (drive) (1) DACK (host) DIOW (host) DIOR (host) IORDY (drive) DATA [ 15:0 ] (drive 2:0 ] and CS [ 1:0 ] (1) Programmable polarity: shown as active LOW. Fig 31. UDMA timing: drive initiating ...
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Philips Semiconductors DREQ (drive) (1) DACK (host) LOW DIOW (host) IORDY DIOR DATA [ 15:0 ] (1) Programmable polarity: shown as active LOW. Fig 33. UDMA timing: receiver pausing a burst. DREQ (drive) (1) DACK (host) DIOW (host) DIOR (host) ...
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Philips Semiconductors DREQ (drive) (1) DACK (host) DIOW (host IORDY (drive DIOR (host) DATA [ 15:0 ] (host 2:0 ] and CS [ 1:0 ] (1) Programmable polarity: shown as active LOW. Fig 35. ...
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Philips Semiconductors DREQ (drive) (1) DACK (host) DIOW (host) IORDY (drive) t d12 DIOR (host) DATA [ 15:0 ] (host 2:0 ] and CS [ 1:0 ] (1) Programmable polarity: shown as active LOW. Fig 37. UDMA timing: ...
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Philips Semiconductors Table 80: UDMA mode timing parameters V = 4 GND amb Symbol Parameter t ready to final strobe edge delay d9 t DACK off to IORDY high-Z delay d10 ...
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Philips Semiconductors 16. Test information The dynamic characteristics of the analog I/O ports ( were determined using the circuit shown in Fig 40. Load impedance for D and D pins (full-speed mode). 9397 750 13462 Product data D.U.T ...
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Philips Semiconductors 17. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...
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Philips Semiconductors 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors • • During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive ...
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Philips Semiconductors [3] [4] [5] [6] [7] [8] [9] 9397 750 13462 Product data These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected ...
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Philips Semiconductors 19. Revision history Table 82: Revision history Rev Date CPCN 06 20041223 200412021 05 20030226 - 04 20020718 - 03 20020218 - 02 20001023 - 01 20001004 - 9397 750 13462 Product data Description Product data (9397 750 ...
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Philips Semiconductors 20. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...
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Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . ...