UPD720100AGM-8EY Renesas Electronics America, UPD720100AGM-8EY Datasheet
UPD720100AGM-8EY
Specifications of UPD720100AGM-8EY
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UPD720100AGM-8EY Summary of contents
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The PD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The interface and ...
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BLOCK DIAGRAM PME0 INTA0 WakeUp_Event OHCI Host Controller #1 PHY Port 1 Port 2 2 PCI Bus INTB0 PCI Bus Interface WakeUp_Event Arbiter OHCI Host Controller #2 Root Hub Port 3 Port 4 USB Bus Data Sheet S15535EJ3V0DS µ PD720100A ...
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PCI Bus Interface : handles 32-bits 33 MHz PCI Bus master and target function which comply with PCI specification release 2.2. The number of enabled ports are set by bit in configuration space. Arbiter : arbitrates among two OHCI Host ...
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PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) (24 × 24) µ PD720100AGM-8ED µ PD720100AGM-8EY µ PD720100AGM-8EY NTEST1 NTEST2 TEST XT1/SCLK 5 XT2 LEGC VCCRST0 SMI0 IRI1 IRI2 IRO1 15 IRO2 A20S ...
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Pin No. Pin Name Pin No NTEST1 42 3 NTEST2 43 4 TEST 44 5 XT1/SCLK 45 6 XT2 46 7 LEGC VCCRST0 50 11 ...
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FBGA (15 × 15) µ PD720100AS1-2C µ PD720100AS1-2C 141 142 143 144 28 87 140 27 86 139 26 85 138 25 84 137 ...
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Pin No. Pin Name Pin No SMC 47 4 AD20 48 5 AD18 49 6 CBE20 50 7 DEVSEL0 DD_PCI 9 SERR0 ...
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PIN INFORMATION Pin Name I/O Buffer Type PCI I/O CBE (3 : 0)0 I PCI I/O PAR I PCI I/O FRAME0 I PCI I/O IRDY0 I/O ...
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Pin Name I/O Buffer Type RREF A Analog PC1 A Analog PC2 A Analog NTEST(2:1) I Input with 12 kΩ Pull down R SMC I Input with 50 kΩ Pull down R SIN/TIN I Input with 50 kΩ Pull down ...
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ELECTRICAL SPECIFICATIONS 2.1 Buffer List • input buffer with Pull down resister NTEST1, NTEST2, TEST, SMC, SIN/TIN, SRMOD, AMC, SCK/TCLK, CLKSEL, TEB • output buffer SOT/TOUT ( mA), SRCLK (I OL • 3 ...
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Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage V DD Input voltage V I Output voltage V O Operating temperature T A Storage temperature T stg Terms Used in Recommended Operating Range Parameter Symbol Power ...
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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage DD_PCI Input voltage buffer V I Input voltage, 3.3 V buffer V I Output voltage buffer V O Output voltage, ...
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DC Characteristics (V = 3 Control Pin Block Parameter Off-state output current Output short circuit current Low-level output current 3.3 V Low-level output current 3.3 V Low-level output current 5.0 V Low-level output current 5.0 ...
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USB Interface Block Parameter Serial Resistor between DP (DM) and RSDP (RSDM). Output pin impedance Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential Common mode Range Output Levels for ...
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Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range -1.0 0.0 0.2 0.4 0.6 0.8 1.0 Input Voltage Range (Volts) Figure 2-2. Full-speed Buffer -3.3 V -2 Min. Max. ...
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Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 Level Figure 2-5. Receiver Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω Pin Capacitance Parameter Input capacitance Output capacitance I/O capacitance PCI input ...
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Power Consumption Parameter Symbol Power Consumption P The power consumption under the state without suspend. WD0-0 Device state = D0, All the ports does not connect to any function. P The power consumption under the state without suspend. WD0-2 Device ...
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System Clock Ratings Parameter Clock frequency Clock Duty cycle Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or Oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply ...
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AC Characteristics (V = 3 PCI Interface Block Parameter PCI clock cycle time PCI clock pulse, high-level width PCI clock pulse, low-level width PCI clock, rise slew rate PCI clock, fall slew rate PCI reset ...
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USB Interface Block Parameter Low Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Differential Rise and Fall Time matching Low-speed Data Rate Source Jitter Total (including frequency tolerance): To Next Transition For Paired Transitions Source ...
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Parameter High-speed Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Driver waveform High-speed Data Rate Microframe Interval Consecutive Microframe Interval Difference Data source jitter Receiver jitter tolerance Hub event Timings Time to detect a downstream ...
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Figure 2-6. Transmit Waveform for Transceiver at DP/DM Level 1 Point 1 Level 2 0% Figure 2-7. Transmitter Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω 22 Point 3 Point 4 Point 2 Point 5 Point ...
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Timing Diagram PCI Clock 0.6V DD 0.5V DD 0.4V DD 0.3V DD 0.2V DD PCI Reset PCLK PWR_GOOD VBBRST0 PCI Signals PCI Output Timing Measurement Condition PCLK output delay output t cyc t t high low 100 ms (typ.) t ...
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PCI Input Timing Measurement Condition PCLK input USB Differential Data Jitter for Low-/full-speed t PERIOD Differential Data Lines USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed t PERIOD Crossover Point Differential Data Lines Diff. Data-to- ...
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USB Receiver Jitter Tolerance for Low-/full-speed t PERIOD Differential Data Lines Low-/full-speed Disconnect Detection D+/D- V IZH (min D-/ Device Disconnected Full-/high-speed Device Connect Detection Device Connected ...
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Low-speed Device Connect Detection Device Connected DCNN Connect Detected Data Sheet S15535EJ3V0DS µ PD720100A ...
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PACKAGE DRAWING 160-PIN PLASTIC LQFP (FINE PITCH) (24x24 120 121 160 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC LQFP (FINE PITCH) (24x24) 120 121 160 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC FBGA (15x15 Index mark φ ...
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RECOMMENDED SOLDERING CONDITIONS µ The PD720100A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of Macrh, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC ...