NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 10

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Tables
10
11-2 Intel® 5000Z Chipset MCH Ballout Center (Top View)........................................... 492
11-3 Intel 5000Z Chipset MCH Ballout Right Side (Top View) ........................................ 493
11-4 Bottom View ................................................................................................... 530
11-5 Top View ........................................................................................................ 531
11-6 Package Stackup ............................................................................................. 532
11-7 Notes ............................................................................................................. 533
1-1
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10 Device 0, Function 0: PCI Express Interconnect-Built-In-Self-Test
3-11 Device 2-3, Function 0: PCI Express PCI Space ......................................................58
3-12 Device 2-3, Function 0: PCI Express Extended Registers .........................................59
3-13 Device 2-3, Function 0: PCI Express IBIST Registers ..............................................60
3-14 Device 4, Function 0: PCI Express PCI Space .........................................................61
3-15 Device 4, Function 0: PCI Express Extended Registers ............................................62
3-16 Device 4, Function 0: PCI Express IBIST Registers .................................................63
3-17 Device 5-7, Function 0: PCI Express PCI Space ......................................................64
3-18 Device 5-7, Function 0: PCI Express Extended Registers .........................................65
3-19 Device 5-7, Function 0: PCI Express IBIST Registers ..............................................66
3-20 Device 9, Function 0: AMB Switching Window Registers ..........................................66
3-21 Device 16, Function 0: Processor Bus, Boot, and Interrupt ......................................67
3-22 Device 16, Function 1: Memory Branch Map, Control, Errors ....................................68
3-23 Device 16, Function 2: RAS .................................................................................69
3-24 Device 21, 22, Function 0: FB-DIMM Map, Control, RAS ..........................................70
3-25 Device 21, Function 0: FB-DIMM 0 IBIST Registers.................................................71
3-26 Device 21, Function 0: FB-DIMM 1 IBST Registers .................................................72
3-27 Device 22, Function 0: FB-DIMM 2 IBST Registers ..................................................73
3-28 Device 22, Function 0: FB-DIMM 3 IBIST Registers.................................................74
3-29 Address Mapping Registers .................................................................................83
3-30 Register Offsets in AMB Memory Mapped Registers Region ......................................94
3-31 XTPR Index ..................................................................................................... 101
3-32 When Will a Intel 5000P Chipset PCI Express Device be Accessible?........................ 102
3-33 Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data
3-1
3-34 IV Handling and Processing by MCH ................................................................... 137
3-35 Maximum Link Width Default Value for Different PCI Express Ports ......................... 147
Related Documents ............................................................................................21
Signal Naming Conventions.................................................................................26
Buffer Signal Types ............................................................................................26
Power Up and Hard Reset Timings........................................................................40
Critical Intel® 5000P Initialization Timings ............................................................41
Configuration Address Bit Mapping .......................................................................50
Memory Control Hub ESI Device Identification .......................................................51
Functions Specially Handled by the MCH ...............................................................52
Access to “Non-Existent” Register Bits ..................................................................52
I/O Address: CF8h .............................................................................................53
I/O Address: CFCh .............................................................................................53
Mapping for Fixed Memory Mapped Registers.........................................................54
Device 0, Function 0: PCI Express PCI Space .........................................................55
Device 0, Function 0: PCI Express Extended Registers ............................................56
(IBIST) Registers...............................................................................................57
Parity Error RAS Handling ................................................................................. 114
GIO Port Mode Selection ................................................................................... 125
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet