NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 100

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.5.6
3.8.6
3.8.6.1
3.8.6.2
100
BOFL[3:0] - Boot Flag Register
These registers can be used to select the system boot strap processor or for other cross
processor communication purposes. When this register is read, the contents of the
register is cleared. Therefore, a processor that reads a non-zero value owns the
semaphore. Any value can be written to this register at any time.
An example of usage would be for all processors to read the register. The first one that
gets a non-zero value owns the semaphore. Since the read clears the value of the
register, all other processors will see a zero value and will spin until they receive further
notification. After the winning processor is done, it writes a non-zero value of its choice
into the register, arming it for subsequent uses. These registers are also aliased to fixed
memory I/O addresses.
Control and Interrupt Registers
PROCENABLE: Processor Enable Global Control
The two FSBEN bits are used to enable or disable frontside bus arbitration. When
frontside bus arbitration is disabled the processor is effectively disabled.
FSBS[1:0] - Processor Bus Status Register
This register holds status from the Processor Busses.
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
31:0
31:5
4:3
1:0
Bit
Bit
2
16
F0h
RCW
Attr
RWST
RWST
Attr
16
0
C0h, C4h, C8h, CCh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
RV
RV
A5A5A5A5h
Default
Default
3fAh
11
0h
0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SemaVal: Semaphore Value
Can be written to any value. Value is cleared when there is a read.
Reserved.
FSBEN: FSB1 and FSB0 Enable
The field is defined as the following:
00: reserved
01: FSB1 is disabled. FSB0 is enabled.
10: FSB1 is enabled. FSB0 is disabled.
11: FSB1 is enabled. FSB0 is enabled. (default)
Hard-reset is needed after changing value in this register.
SFBYPASS: Snoop Filter Bypass
0: SF is enabled
1: SF is disabled
Note: The output of the fuse “SF CHOP” is gated appropriately with this
register field viz. SFBYPASS for further internal decoding by Intel 5000P
Chipset MCH. The fuse has overriding effect.
Reserved.
Description
Description
Register Description